Invasion: Application-Driven Resource Management for Future MPSoCs - PowerPoint PPT Presentation

Invasion: Application-Driven Resource Management for Future MPSoCs Management for Future MPSoCs J T i h 12th OC C ll J. Teich, 12th OC Colloquium, Nuremberg, 15. September 2011 i N b 15 S t b 2011

Outline • What is Invasive Computing? – Uniquitousness of parallel computers – Challenges in the year 2020 – Vision and Potentials • Scientific Work Program – Basics: Resource-Aware Programming, Algorithms, Complexity – Architectures: Reconfigurability and Decentralized Resource Management A hi R fi bili d D li d R M – Tools: Compiler, Simulation Support and Run-Time System – Applications: Robotics, Scientific Computing • Structure, Chances and Goals – Project structure – Funded Institutions and Researchers F d d I tit ti d R h – Demonstrator Roadmap – Impact and Risks Folie 2

Ubiquitousness of parallel computers Sony Playstation 3, IBM Cell 9 Cores Nvidia Fermi: 512 Cores I t l SCC 48 Intel SCC: 48 cores Folie 3

Ubiquitousness of parallel computers Source: Hardware/Software Co-Design, Univ. of Erlangen-Nuremberg, Jan 2009. Programmable 5x5 core MPSoC for image filtering. Technology: CMOS 1.0 V, 9 metal Layers 90nm standard cell design. VLIW memory/PE: 16x128, FUs/PE: 2xAdd, 2xMul, 1xShift, 1xDPU. Registers/PE: 15. Register file/PE: 11 read/ 12 write ports. Configuration Memory: 1024x32 = 4KB. Operating frequency: 200 MHz. Peak Performance: 24 GOPS. Power consumption: 132,7 mW @ 200 MHz (hybrid clock gating). Power efficiency: 0,6 mW/MHz. Folie 4

Challenges in the year 2020 Architectures Programming Architectures, Programming and Management of Applications for 1000s of Applications for 1000s of Processors in 2020? Folie 5

Challenges in the year 2020 • Complexity – How to map dynamically applications onto 1000 or more processors while considering memory, communication and computing resource constraints? • Adaptivity – How and to what degree shall algorithms and architectures be adaptable (HW/SW, bit/word/loop/thread/process-level)? • Scalability – How to specify and/or generate programs that may run without (great) modifications on either 1,2,4, or N processors? • Physical Constraints Physical Constraints – Low power, performance exploitation, management overhead • Reliability and Fault-Tolerance – Necessity for compensation of process variations as well as temporal and permanent N it f ti f i ti ll t l d t defects Folie 6

Invasion: Example RAM RAM CPU0 CPU0 I/O I/O RAM RAM R Bus Bus RAM RAM RAM RAM RAM RAM CPU1 CPU1 CPU2 CPU2 Bridge Bridge B id B id RAM RAM RAM RAM Bus Bus Bus Bus RAM RAM RAM RAM CPU3 CPU3 CPU4 CPU4 Folie 8

Considered Abstraction Levels Hw + S w Control process-level, thread-level Multi- Core Hw-Ctrl.+ Func. w Ct l. u c. loop-level loop level FOR i=0 TO N DO Processor FOR j =0 TO M DO Array … Hw-Ctrl. / VLIW instruction-level ADD R1, R2, R3 FUs MUL R4, R1, $4 JMP $42 H Hw-Ctrl. / VLIW Ct l / VLIW word-level, bit-level 01010001101010101010 S W- Units 10101010100011111111 Folie 9

Vision and Potentials • Run-Time Scalability – Today´s parallel programs are in general not able to adapt themselves to the – Today s parallel programs are in general not able to adapt themselves to the current availablity of resources. – Today´s computer architectures do not support any application-controlled resource reservation. esou ce ese a o • Dynamic Self-Optimization possible through Invasion wrt. – Resource Utilization Resource Utilization – Power Consumption (Temperature Management) – Performance • Tolerance of Failures and Defects – Today´s parallel programs just would not run (correctly) any more! • Robustness – Applications tolerate a variable availability of resources – Applications tolerate a variable availability of resources Folie 10

Potential: Resource Utilizations up to 100% RAM RAM CPU0 CPU0 I/O I/O RAM RAM R Bus Bus RAM RAM RAM RAM RAM RAM CPU1 CPU1 CPU2 CPU2 B id B id Bridge Bridge RAM RAM RAM RAM Bus Bus Bus Bus RAM RAM RAM RAM CPU3 CPU3 CPU4 CPU4 Folie 11

Potential: Power and Temp. Management RAM RAM CPU0 CPU0 CPU0 CPU0 CPU0 CPU0 I/O I/O RAM RAM R Bus Bus RAM RAM RAM RAM RAM RAM CPU1 CPU1 CPU1 CPU1 CPU1 CPU1 CPU2 CPU2 CPU2 CPU2 CPU2 CPU2 B id B id Bridge Bridge RAM RAM RAM RAM Bus Bus Bus Bus RAM RAM RAM RAM CPU3 CPU3 CPU4 CPU4 Folie 12

Potential: Performance Gain/Tradeoff RAM RAM CPU0 CPU0 I/O I/O RAM RAM R Bus Bus RAM RAM RAM RAM RAM RAM CPU1 CPU1 CPU2 CPU2 B id B id Bridge Bridge RAM RAM RAM RAM Bus Bus Bus Bus RAM RAM RAM RAM CPU3 CPU3 CPU4 CPU4 Folie 13

Potential: Robustness and Fault-Tolerance RAM RAM CPU0 CPU0 I/O I/O RAM RAM R Bus Bus RAM RAM RAM RAM RAM RAM CPU1 CPU1 CPU2 CPU2 B id B id Bridge Bridge RAM RAM RAM RAM Bus Bus Bus Bus RAM RAM RAM RAM CPU3 CPU3 CPU4 CPU4 Folie 14

Outline • What is Invasive Computing? – Uniquitousness of parallel computers – Challenges in the year 2020 – Vision and Potentials • Scientific Work Program – Basics: Resource-Aware Programming, Algorithms, Complexity – Architectures: Reconfigurability and Decentralized Resource Management A hi R fi bili d D li d R M – Tools: Compiler, Simulation Support and Run-Time System – Applications: Robotics, Scientific Computing • Structure, Chances and Goals – Project structure – Funded Institutions and Researchers F d d I tit ti d R h – Demonstrator Roadmap – Impact and Risks Folie 15

Basic Functionality of Invasive Programs • Invade Construct(s) for request and Construct(s) for request and reservation of resources (processors, memory, i interconnect) ) • Infect Construct(s) for programming, ( ) p g g, resp. configuration of resources (processors, memory, interconnect) for special services interconnect) for special services • Retreat Concept invade-let (i-let) Construct(s) for release of resources (processors, memory, ( interconnect) Folie 16

Basics of Invasive Programming i-let - permission - speed - invade - utilization - infect - power/ - retreat temp temp - … - fault/error Folie 17

Project Area A – Basics • Programming and Language Issues: – Finding and classification of elementary Finding and classification of elementary (basic) constructs for invasive programs (the invasive command space ) [A1] – Definition of an abstract kernel language Definition of an abstract kernel language (syntax, semantics, type system) [A1] – Embedding of command set into programming language(s) [A1] • Mathematical Models for Effifiency and Utilization Analysis of invasive applications [A1] • Algorithm Engineering: – Complexity and cost invasive algorithms [A1] – Complexity and cost invasive algorithms [A1] – Scheduling and Load Balancing [A3] Folie 22

Basic Invasive Programming Constructs • Invade • Infect – Allocation and reservation of system y – Copying program code and data py g p g resources to the claimed resources • Processors – Parallel execution of the program i-lets (code + data) • Communication channels • Memory • Retreat – Returns a claim (allocated resources) – Frees occupied resources Frees occupied resources – Depends on the applications demand Depends on the applications demand of parallelism – Depends on the current state of the resources (resource-aware) ( ) Folie 23

Invasive Programming Constructs • Definitions – i-let: i l t • A piece of a program for invasive-parallel execution (code+data) – claim: • Set of allocated resources (processors, memory, communication) • Realization – Using existing parallel programming languages, instead of designing a new language g g g g – Decision: Extension of X10 programming language – Using X10 as base language for invasive computing – Library-based approach Library based approach Folie 24

Languages and APIs for Parallel Programming Folie 25

Outline • Invasive Programming in X10 – Introduction to X10 – Invasive Programming Library • Simulation of Invasive Programs and MPSoC architectures – Goals – Simulation Model – Case Study – Future Work Folie 26

X10 Programming Language • X10 Programming Language – Parallel object-oriented programming language – Parallel, object-oriented programming language – Developed by IBM (since 2004) • General Properties G l P ti – Supports distributed, heterogeneous processor and memory architectures – Syntax between Java and Scala – OO language features: • Classes, objects, inheritance, generic types – Functional language features: • Type inference, anonymus functions, closures, pattern matching – Parallel constructs: • Concurrency, synchronization, distribution, atomicity y, y , , y – PGAS Programming Model Folie 27