I A-64, the Trillian project, and CERNs involvement CERN - PowerPoint PPT Presentation

S.Jarp CERN I A-64, the Trillian project, and CERN’s involvement CERN Computing Seminar 1 17 May 2000

CERN Main justifications S.Jarp � Contribute to Open Source � Be fully prepared to evaluate I A-64 for LHC computing � I nfluence key hardware/ software vendors � CERN benchmarks for compiler improvements, etc. 2 17 May 2000

CERN Agenda S.Jarp � What is this new architecture (I A-64)? � History � Projects � Future objective � LHC Testbed/ Grids � Conclusions 3 17 May 2000

I A-64 Architecture 4

CERN Some definitions S.Jarp � We define: � I A-32 � as “x86”, I .e. I ntel’s current 32-bit architecture � I A-64 � as I ntel’s new 64-bit architecture � I A-XX � “XX” refers to integer registers � So, I A-64 enables 64-bit “long” and “pointer” variables � I n other words: Linux’s “LP64” programming model � Note: � I n a 64-bit architecture, one can normally still use 32-bit “int” variable and 32-bit pointers (in a 4 GB Addr. Space) � Floating-point registers are already 80-bit on I A-32 Supporting 32-bit “float”, 64-bit “double”, and 80-bit “long double” � 5 17 May 2000

CERN I A-64 Highlights S.Jarp � Key I nnovations: � Rich I nstruction Set � Bundled (parallel) Execution � Predicated I nstructions � Large Register Files � Register Stack � Rotating Registers � Software Pipelined Loops � Control/ Data Speculation � Cache [I / D] Control I nstructions � High-precision 82-bit Floating-Point 6 17 May 2000

CERN Compared to I A-32 S.Jarp � Many advantages: � Clear, explicit programming � After all, this is EPI C: “Explicitly Parallel I nstruction Computing” � � Register-based programming � Keep everything in registers (As long as possible) � 128 integer + 128 floating-point register � Architected renaming (“Rotation”) � Architectural support for software pipelining � “Modulo scheduling” � All instructions (almost) can be predicated � 64 1-bit registers (“Fire”/ ”Do not fire”) � Much more general than CONDI TI ONAL MOVES 7 17 May 2000

CERN I nstruction Bundle S.Jarp � ‘Packaging entity’ (16 bytes): � 3 * 41 bit I nstruction Slots � 5 bits for Template: � Typical examples: � MFI (Memory/ FLP/ I nteger) � MI B (Memory/ I nteger/ Branch) � I ncluding “stop” bit Slot 2 Slot 1 Slot 0 T 8 17 May 2000

CERN I nstruction Delivery S.Jarp � Must match (in I tanium): � 6 instructions with 9 issue ports � w/ corresponding execution units attached S0 S1 S2 S0 S1 S2 Dispersal network (template interpretation) M0 M1 F0 F1 I 0 I 1 B0 B1 B1 9 17 May 2000

CERN SW Pipelined Loops S.Jarp � Graphical example � 7 loop traversals desired � Skewed execution � Stage 2 relative to Stage 1 � Stage 3 relative to Stage 2 Main loop Epilogue Completed Stages Stage 3 Stage 2 Stage 1 Time See presentation in the references for further details 10 17 May 2000

The History 11

CERN History - 1 HP architect: S.Jarp Bill Worley � Visit to HP Labs in November 1992 � Great secret: The PA-RI SC successor is under development: � PA-WW Mathlib expert: Clemens Roothaan 12 17 May 2000

CERN History - 2 S.Jarp I ntel architect: Gadi Singer � 1994 – 1998 � Architecture is renegotiated between HP and I NTEL � New name: I A-64 � Merge of ideas � As of 1997/ 98 � Huge effort across I T industry to prepare � OS, compilers, libraries, middleware, applications � Mid-1999 � First chip becomes reality: � Merced � � I tanium 13 17 May 2000

CERN CERN/ HP projects S.Jarp � 1994 – 1997: � Review of architecture � This “project” was so secret that hardly anybody knew about it ! � 1998 – 1999: � Joint projects � HP: I mplement a vector math library � CERN: Random Number Generators (in vector mode) � 1999 – � Linux/ I A-64 porting project � Which grew into Trillian 14 17 May 2000

TRI LLI AN Project 15

CERN Trillian S.Jarp � The porting goals: � Provision of: � Full support of hardware, firmware, boot process � The PC platform has undergone a complete review with I A-64. � Kernel � Exploiting I A-64 features, such as huge address spaces, large page sizes. Support of I A-32 binaries. � Native compilers � I nitially gcc � Libraries � glibc, optimised libm, etc. � Middleware � X-server, Performance Counter Library, etc. 16 17 May 2000

CERN Trillian (I nitial phase) S.Jarp � Leading I T companies + CERN: � Port basic OS, utilities, compilers, libraries � CERN, Cygnus, HP, I BM, I NTEL, SGI , and VA Linux � CERN team: � Responsible for glibc (generic/ specific) � Shared library support � Testing environment: � HP simulator (on top of Linux/ I A-32) � I ntel simulator also available on top of Windows/ NT � � Goal: � Be ready for first hardware with a fully functional port 17 17 May 2000

CERN Trillian (Phase 2) S.Jarp � New companies joined: � First, distributors joined: Caldera, RedHat, SuSE, and Turbolinux. � and very recently: Linuxcare and NEC � I ntel � Distributed real prototype systems � “Bigsur” - 2-way workstation � “Lion” - 4-way server � Trillian was ready: � Native kernel/ compiler/ libs/ etc. � SGI added compilers: Other compilers are expected to come � sgicc, sgiCC, sgif90 18 17 May 2000

CERN Trillian (now) S.Jarp � Final phase: � Glibc � Stabilise and fix bugs � Complete optimisation of time-critical routines: � Memory (e.g.memcpy) and String (e.g. strcpy) routines � Move from glibc 2.1 to 2.2 � Porting real applications: � Solution stacks: � GEANT4 (including CLHEP) using g+ + and sgiCC � SI XTRACK using sgif90 � Several benchmarks already “running” � Aim: � Be ready at first shipment (3Q 2000?) � With well-running applications 19 17 May 2000

CERN Kernel S.Jarp � Now fully integrated in standard distribution � Layout: Application Application X11 1 2 Subsystem System Calls Device Network File I A-32 drivers protocols Systems Subsystem Signal Process Virtual Mem subsystem subsystem subsystem I nterrupt Trap handling subsystem I nterrupt Vector Table 20 17 May 2000

CERN Compiler technology S.Jarp � As critical as it was for “vector supercomputing” � Desired goal: � Loops optimised through Software Pipelining � Currently: � This seems easier for FORTRAN than C+ + � SI XTRACK (FORTRAN) � Loop optimisation takes place � GEANT4 � Deep level of method nesting makes the task harder � Too early to draw any conclusions 21 17 May 2000

2005 Projections I A-64 and LHC 22

CERN I ntel’s project future - 1 S.Jarp . . . . . . . . Madison . . . . IA-64 Perf IA-64 Perf Deerfield IA-64 Price/Perf Perf IA-64 Price/ Performance McKinley . . . . . . Future IA-32 Itanium Processor Foster Cascades First price/ performance Pentium III version Processor ’99 ’00 ’01 ’02 .25µ .18µ .13µ 23 17 May 2000

CERN I ntel’s projected future - 2 S.Jarp 120 100 80 LHC 60 IA-64 40 (percent of total) 20 Pre LHC 0 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 q q q q q q q q Forecast by 1 1 1 1 1 1 1 1 Microprocessor Report 24 17 May 2000

CERN st or age net wor k 12 Gbps processor S.Jarp s CERN … … … … t apes 5600 processors 1. 5 Gbps 1400 boxes 160 clusters 0. 8 40 sub- f arms Gbps 6 Gbps* 8 Gbps 24 Gbps* f ar m net wor k 960 Gbps* 0. 8 Gbps (daq) 100 drives CMS Of f line Farm LAN- WAN routers at CERN cir ca 2006 250 Gbps 0.5 M SPECint95 st or age net wor k 5 Gbps > 5K processors 0. 8 Gbps 5400 0.5 PByte disk disks 340 >5K disks arrays ……. disks .. 25 17 May 2000 lmr f or Monarc st udy- april 1999

CERN Possible Grid structure S.Jarp Tier 1 RC CERN ?? full ESD full data . . 622 Mpbs links + air freight Tier 1 RC University/ Tier 1 RC US Department cluster Italy Tier 1 RC full ESD full ESD France 622 Mpbs links full ESD University/ desktop Department cluster University/ desktop Department cluster desktop .. desktop 26 17 May 2000

CERN Conclusions S.Jarp � Exciting new architecture � A full-fledged Linux port is available � I A-64 should, some day, replace I A-32 � but watch out for ‘inflection points’ � Understand full potential � HEP’s huge source base; Some hand-coded routines � Working directly with the ‘creators’ � HP, I NTEL, and many others � Maintain CERN in a leading role � With top I T companies � I nside key projects, like the LHC Testbed and proposed European GRI D project 27 17 May 2000

CERN Further references S.Jarp Trillian: � http:/ / www.linuxia64.org/ [Trillian home page] � http:/ / www.turbolinux.com/ ia64.html [Linux distribution] � http:/ / oss.sgi.com/ projects/ Pro64/ [Linux compilers] � At CERN: � http:/ / nicewww.cern.ch/ ~ sverre/ Linux_I A64_project.html � I A-64 programming: � http:/ / developer.intel.com/ design/ I a-64/ [I ntel documentation] � http:/ / nicewww.cern.ch/ ~ sverre/ I A64_1.pdf [My tutorial] � http:/ / nicewww.cern.ch/ ~ sverre/ I ntel_SW_Pipelining_Notes.pdf � Kernel: � http:/ / www.kernel.org/ pub/ linux/ kernel/ ports/ ia64 [Kernel source] � http:/ / www.linuxia64.org/ logos/ I A64linuxkernel.PDF [Presentation] � 28 17 May 2000