Hardware Support for ACID Transactions in Persistent Memory Arpit Joshi , Vijay Nagarajan, Marcelo Cintra, Stratis Viglas NVMW 2019
Persistent Memory Systems L1 L1 LLC Persistent Memory � 2
Persistent Memory Systems L1 L1 • Persistent Memory - Non-volatility over the memory bus - Load/Store interface to persistent data LLC Persistent Memory � 2
Persistent Memory Systems L1 L1 • Persistent Memory - Non-volatility over the memory bus - Load/Store interface to persistent data LLC System Crashes Persistent Memory � 2
Persistent Memory Systems L1 L1 • Persistent Memory - Non-volatility over the memory bus - Load/Store interface to persistent data LLC System Crashes • Crash Consistency - Is the persistent state consistent? Persistent Memory - Programming Model: ACID Transactions � 2
Persistent Memory Systems L1 L1 • Persistent Memory “Ensuring failure atomicity for all this computation without - Non-volatility over the memory bus failure-atomic transactions is practically infeasible, if not - Load/Store interface to persistent data impossible.” LLC System Crashes Marathe et al. [HotStorage’17] • Crash Consistency - Is the persistent state consistent? Persistent Memory - Programming Model: ACID Transactions � 2
Persistent Memory Systems L1 L1 • Persistent Memory “Ensuring failure atomicity for all this computation without - Non-volatility over the memory bus failure-atomic transactions is practically infeasible, if not - Load/Store interface to persistent data impossible.” LLC System Crashes Marathe et al. [HotStorage’17] • Crash Consistency - Is the persistent state consistent? Persistent Memory - Programming Model: ACID Transactions How fast can we support ACID? � 2
ACID Transactions L1 L1 LLC Persistent Memory � 3
ACID Transactions Atomic Visibility L1 L1 LLC Persistent Memory � 3
ACID Transactions Atomic Visibility L1 L1 LLC Persistent Memory Atomic Durability � 3
ACID Transactions Atomic Visibility L1 L1 STM Locks HTM LLC Persistent Memory Atomic Durability � 3
ACID Transactions Atomic Visibility L1 L1 STM Locks HTM LLC Check- H/W S/W Logging pointing Logging Persistent Memory Atomic Durability � 3
ACID Transactions Atomic Visibility L1 L1 STM Locks HTM LLC Check- H/W S/W Logging pointing Logging Persistent Memory Atomic Durability � 3
Atomic Visibility: HTM � 4
Atomic Visibility: HTM • Commercial HTMs [Intel, IBM] L1 Cache Cache Line R W A = 15 1 B = 20 1 � 4
Atomic Visibility: HTM • Commercial HTMs [Intel, IBM] L1 Cache - Version Management : read/write sets in L1 cache Cache Line R W A = 15 1 B = 20 1 � 4
Atomic Visibility: HTM • Commercial HTMs [Intel, IBM] L1 Cache - Version Management : read/write sets in L1 cache Cache Line R W - Conflict Detection : piggy back on the A = 15 1 coherence protocol B = 20 1 � 4
Atomic Visibility: HTM • Commercial HTMs [Intel, IBM] L1 Cache - Version Management : read/write sets in L1 cache Cache Line R W - Conflict Detection : piggy back on the A = 15 coherence protocol B = 20 - Commit : make updates non-speculative � 4
Atomic Visibility: HTM • Commercial HTMs [Intel, IBM] L1 Cache - Version Management : read/write sets in L1 cache Cache Line R W - Conflict Detection : piggy back on the coherence protocol B = 20 - Commit : make updates non-speculative - Abort : invalidate write set � 4
Atomic Visibility: HTM • Commercial HTMs [Intel, IBM] L1 Cache - Version Management : read/write sets in L1 cache Cache Line R W - Conflict Detection : piggy back on the coherence protocol B = 20 - Commit : make updates non-speculative - Abort : invalidate write set Write-sets in commercial HTMs limited by the size of the L1 cache. � 4
Atomic Durability: Logging � 5
Atomic Durability: Logging Persistent Memory • Logging for durability [ Doshi’16, Joshi’17, Shin’17, Ogleari’18 ] In-place Values A = 10 B = 20 C = 30 � 5
Atomic Durability: Logging Persistent Memory • Logging for durability [ Doshi’16, Joshi’17, Shin’17, Ogleari’18 ] In-place Values Transaction Log A = 10 A = 15 - Write a log entry for every update B = 20 B = 25 C = 30 � 5
Atomic Durability: Logging Persistent Memory • Logging for durability [ Doshi’16, Joshi’17, Shin’17, Ogleari’18 ] In-place Values Transaction Log A = 15 - Write a log entry for every update B = 25 - Commit : Update the values in-place C = 30 � 5
Atomic Durability: Logging Persistent Memory • Logging for durability [ Doshi’16, Joshi’17, Shin’17, Ogleari’18 ] In-place Values Transaction Log A = 15 A = 10 - Write a log entry for every update B = 25 B = 20 - Commit : Update the values in-place C = 30 - Abort : Undo any in-place updates � 5
Atomic Durability: Logging Persistent Memory • Logging for durability [ Doshi’16, Joshi’17, Shin’17, Ogleari’18 ] In-place Values Transaction Log A = 15 A = 10 - Write a log entry for every update B = 25 B = 20 - Commit : Update the values in-place C = 30 - Abort : Undo any in-place updates In-place updates in the critical path of commit High memory write bandwidth requirement � 5
ACID = HTM + Logging Goals: - Support fast commits - Minimise memory bandwidth consumption - Extend the supported transaction size - Maintain the simplicity of commercial HTMs � 6
DHTM: Durable Hardware Transactional Memory L1 L1 Log Writes LLC Persistent Memory � 7
DHTM: Durable Hardware Transactional Memory L1 L1 Commercial HTM + Hardware Redo Log Log Writes LLC Persistent Memory � 7
DHTM: Durable Hardware Transactional Memory L1 L1 Commercial HTM + Hardware Redo Log - H/W Redo Log + Log Buffer Log Writes Reduced memory bandwidth LLC Fast commits Persistent Memory � 7
DHTM: Durable Hardware Transactional Memory L1 L1 Commercial HTM + Hardware Redo Log - H/W Redo Log + Log Buffer Log Writes Reduced memory bandwidth LLC Fast commits - H/W Log + Sticky State Extended transaction size to the LLC Simplicity of commercial HTM Persistent Memory � 7
DHTM: Log Buffer L1 L1 Log Writes LLC Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem Log Writes LLC Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem - write a log entry for every store Log Writes LLC Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem - write a log entry for every store Log Writes - multiple stores create multiple log entries LLC Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem - write a log entry for every store Log Writes - multiple stores create multiple log entries LLC • Solution: Log Buffer Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem - write a log entry for every store Log Writes - multiple stores create multiple log entries LLC • Solution: Log Buffer - track cache lines being modified Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem - write a log entry for every store Log Writes - multiple stores create multiple log entries LLC • Solution: Log Buffer - track cache lines being modified - multiple writes coalesced in a log entry Persistent Memory � 8
DHTM: Log Buffer L1 L1 • Redo Log Bandwidth Problem - write a log entry for every store Log Writes - multiple stores create multiple log entries LLC • Solution: Log Buffer - track cache lines being modified - multiple writes coalesced in a log entry - log entry written to persistent memory on eviction Persistent Memory from log buffer � 8
DHTM: Transaction States � 9
DHTM: Transaction States Begin Transaction Active � 9
DHTM: Transaction States End Transaction & Begin Log Records Transaction Persisted Active Commit � 9
DHTM: Transaction States End Transaction & Begin In-place Data Log Records Transaction Persisted Persisted Commit Active Commit Complete � 9
DHTM: Transaction States End Transaction & Begin In-place Data Log Records Transaction Persisted Persisted Commit Active Commit Complete Abort Conflict � 9
DHTM: Commit Example State L1 Cache Cache Line R W Begin_Transaction Log Buffer Write (A=15) Read (B) Persistent Memory Write (B=25) Transaction Log End_Transaction In-place Values A = 10 A = 10 A = 15 B = 20 B = 25 B = 20 C = 30 � 10
DHTM: Commit Example State L1 Cache Active Cache Line R W Begin_Transaction Log Buffer Write (A=15) Read (B) Persistent Memory Write (B=25) Transaction Log End_Transaction In-place Values A = 10 A = 10 A = 15 B = 20 B = 25 B = 20 C = 30 � 10
DHTM: Commit Example State L1 Cache Active Active Cache Line R W Begin_Transaction Log Buffer A = 15 1 A Write (A=15) Read (B) Persistent Memory Write (B=25) Transaction Log End_Transaction In-place Values A = 10 A = 10 A = 15 B = 20 B = 20 B = 25 C = 30 � 10
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