Design of 2 nd Prototype Architecture Measurements Summary Front–end Electronics for Straw Tube Tracker in PANDA Experiment Dominik Przyborowski , Marek Idzik AGH University of Science and Technology PANDA STT Workshop 10 October 2013, Juelich Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Outline Front–end Specification and Architecture 1 Measurements of 1 st Prototype 2 Design of 2 nd Prototype 3 Summary 4 Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Specification Features CSP with variable gain and time constant CR–RC 2 shaper with variable peaking time Ion tail cancellation circuit with trimming Baseline stabilized by BLH circuit Leading edge discriminator for time and ToT measurements Fast LVDS output Buffered analog output Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Architecture Preamplifier and Shaper Features Schematic diagram Variable charge gain: 0.5 – 4 mV/fC Variable preamp time constant: - 25 – 800 ns - PZC matched to various preamp settings 1 st shaper stage with T P in range 10 – 40 ns Input transistor Drain current = 2 mA W/L = 2000 µ /0.35 µ Transconductance ≈ 26 mS Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Architecture Tail Cancellation and Output stages Schematic diagram - + - + - + Tail cancellation 4 modes of operation: τ 1 & τ 2 TC, only τ 1 TC, only τ 2 TC, CR–RC 2 (no TC) Trimming time constants: τ 1 ∈ 3 – 43 ns (6 bits) τ 2 ∈ 18 – 511 ns (6 bits) Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Architecture Baseline Holder Schematic diagram + K - - + K Components Nonlinear buffer (slew rate limited - OTA 0 and C 0 ) High value tunable active resistor for low pass filter (A. Tajalli, Y. Leblebici, E.J. Brauer, Implementing Ultra-High-Value Floating Tunable CMOS Resistors , Electronics Letters, 2008, pp. 349-350) Current sink controlling current in last stage feedback Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Architecture Leading Edge Discriminator Schematic diagram Stages Two low–gain preamplifing stages Latch stage with histeresis Self–biased amplifier Inverters Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results First prototype basic data Chip size: 1.5 × 1.2 mm 2 AMS 0.35 µ m 2P–4M CMOS Process Four channels Channel size: 200 × 1130 µ m 2 Power consumption: ∼ 15.5 mW/ch + LVDS ∼ 12 mW ≈ 28 mW/ch Peripherals not yet designed, biasing and thresholds setting externally Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Pulse shapes δ pulse response for 10ns T P settings (CR–RC 2 mode – no TC) 1.56 C in = 5.7 (pF) C in = 23 (pF) 1.54 C in = 34 (pF) 1.52 1.5 Output voltage (V) 1.48 1.46 1.44 1.42 1.4 1.38 1.36 1.34 0 10 20 30 40 50 60 70 80 Time (ns) Response slower due to layout parasitics and output buffer performance Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Linearity and Gain Channel modes (CR–RC 2 mode – no Channel uniformity (with TC) TC) 1600 Ch1 Ch2 Ch3 1400 Ch4 K pre = 0.5 (mV/fC) K pre = 2 (mV/fC) 3 Ch5 K pre = 1 (mV/fC) K pre = 4 (mV/fC) Ch6 1200 2.8 Ch7 Ch8 Output Voltage (V) 1000 2.6 2.4 Output Voltage (V) 800 K 1 = 9.5 (mV/fC) K 2 = 10.1 (mV/fC) 2.2 600 K 3 = 10.1 (mV/fC) K .5 q = 3.8 (mV/fC) K 4 = 10.6 (mV/fC) 2 K 5 = 9.6 (mV/fC) K 1 q = 6.9 (mV/fC) 400 K 6 = 9.9 (mV/fC) 1.8 K 7 = 10.3 (mV/fC) K 2 q = 13.2 (mV/fC) K 8 = 10.6 (mV/fC) 200 1.6 K 4 q = 23.4 (mV/fC) 1.4 0 V baseline = 1.186 (V) 0 20 40 60 80 100 120 140 160 1.2 Input Charge (fC) 0 50 100 150 200 250 300 350 400 450 Input Charge (fC) Analog buffer output S–curves measurements Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Noise ENC vs input capacitance ENC vs peaking time 0.7 4370 0.45 2809 pre = 0.5 (mV/fC) K q K pre = 0.5 (mV/fC) pre = 1 (mV/fC) K q K pre = 4 (mV/fC) pre = 2 (mV/fC) K q 0.4 2497 pre = 4 (mV/fC) 0.6 K q 3745 Equivallent Noise Charge (fC) Equivallent Noise Charge (e - ) Equivallent Noise Charge (fC) Equivallent Noise Charge (e - ) 0.35 2185 0.5 3121 0.3 1873 0.4 2497 0.25 1561 0.3 1873 0.2 1248 0.2 1248 0.15 936 0.1 624 0.1 624 0 20 40 60 80 100 5 10 15 20 25 30 35 40 45 Input capacitance (pF) Peaking time (ns) ENC ≈ 1000 e − for default FE settings ( K pre = 2 mV / fC , T P = 10 ns and C in = 25 pF ) Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Tail cancellation Responses for Fe 55 X–rays High rate h3 h3 h3 1.60 Entries Entries 2001 2001 180 non-optimized Mean Mean 361.9 361.9 optimized RMS RMS 192.2 192.2 160 1.56 180 160 140 140 Output Voltage (V) 1.52 120 120 100 Output voltage (mV) 80 1.48 100 60 40 80 20 1.44 0 60 -20 1.40 0 200 400 600 800 1000 1200 40 20 1.34 0 1.32 -20 100 200 300 400 500 600 0 50 100 150 200 250 Time (ns) Time (ns) Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Time resolution Jitter Time walk 40 10 σ = 0.14 (ns) 35 8 30 25 Time walk (ns) 6 Counts 20 4 15 10 2 5 0 0 20 40 60 80 100 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 Time (ns) Input charge (fC) 1–2 ns time precision could be obtained by compensating time walk basing on amplitude information Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Time–over–Threshold 62 60 Time-over-Threshold (ns) 58 56 54 52 50 0 20 40 60 80 100 Input charge (fC) Results achieved for delta pulse and different FEE settings Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Fe 55 X–rays spectrums ToT spectrum Amplitude spectrum Good separation of Fe 55 K– α and escape peaks for both methods Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Baseline Baseline level vs temperature 1.37 1.369 Baseline voltage (V) 1.368 1.367 1.366 1.365 25 30 35 40 45 Temperature ( o C) Measure after output buffer – V gs and β variations Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Measurement results Summary of 1 st prototype 1 st prototype of STT front–end fully functional Variable gain 3 – 24 mV/fC and peaking time ∼ 20 – 40 ns work well ENC ≈ 1000 e − for default conditions ( K pre = 2 mV / fC , T P = 10 ns and C in = 25 pF ) Tail cancellation works and could be trimmed to various types of input signals Readout module with 8 ASICs (32 channels) succesfully used in test-beam The front–end design and performance was presented at TWEPP–2013 Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Design of 2 nd Prototype Features not implemented in 1 st prototype Lack of DACs for baseline control (high baseline dispersion was expected) Longer T P (18 ns) in post–layout simulations Issues found during tests Saturation of preamplifier for large signals Analog buffer not addapted for high capacitive load Planned improvements Implementation of 8 channels Redesign of preamp/shaper for higher speed ( T P =10 ns) DAC addition and BLH modification for uniform baseline Improvement of analog buffer Elimination of saturation for large signals Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
Design of 2 nd Prototype Architecture Measurements Summary Design of 2 nd Prototype Preamplifier and shaper Planned Modifications Complementary architecture with pseudo Class AB Flipped Voltage Follower DC current compensation circuit Variable charge gain: 1, 2 and 4 mV/fC Response rise time ∼ 5 ns (3 × faster) Dominik Przyborowski , Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E
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