Introduction SysML MARTE Code Generation Conclusions and Remarks Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities Marcello Mura Amrit Panda Mauro Prevostini marcello.mura@lu.unisi.ch amrit.panda@lu.unisi.ch mauro.prevostini@unisi.ch ALaRI - University of Lugano 14 March 2008
Introduction SysML MARTE Code Generation Conclusions and Remarks Presentation Outline Introduction 1 SysML 2 MARTE 3 Code Generation 4 5 Conclusions and Remarks
Introduction SysML MARTE Code Generation Conclusions and Remarks Outline Introduction 1 SysML 2 MARTE 3 Code Generation 4 5 Conclusions and Remarks
Introduction SysML MARTE Code Generation Conclusions and Remarks Introduction Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Optimization: Requirements Reverse Engineering. definition/validation Functional Incremental Design evaluation/optimization. Verification Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.
Introduction SysML MARTE Code Generation Conclusions and Remarks Introduction Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Optimization: Requirements Reverse Engineering. definition/validation Functional Incremental Design evaluation/optimization. Verification Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.
Introduction SysML MARTE Code Generation Conclusions and Remarks Introduction Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Optimization: Requirements Reverse Engineering. definition/validation Functional Incremental Design evaluation/optimization. Verification Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.
Introduction SysML MARTE Code Generation Conclusions and Remarks Introduction Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Optimization: Requirements Reverse Engineering. definition/validation Functional Incremental Design evaluation/optimization. Verification Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.
Introduction SysML MARTE Code Generation Conclusions and Remarks Introduction Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Optimization: Requirements Reverse Engineering. definition/validation Functional Incremental Design evaluation/optimization. Verification Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.
Introduction SysML MARTE Code Generation Conclusions and Remarks Modelling Language UML2 Adds new capabilities, achieves greater semantic accuracy and gives better support for code generation. Model Driven Architecture Defines a framework for Code Generation. Platform independent model are initially defined and then such models are refined for the particular platform. Profiles Means of tailoring UML for particular purposes. Extensions of the language can be inserted.
Introduction SysML MARTE Code Generation Conclusions and Remarks Modelling Language UML2 Adds new capabilities, achieves greater semantic accuracy and gives better support for code generation. Model Driven Architecture Defines a framework for Code Generation. Platform independent model are initially defined and then such models are refined for the particular platform. Profiles Means of tailoring UML for particular purposes. Extensions of the language can be inserted.
Introduction SysML MARTE Code Generation Conclusions and Remarks Modelling Language UML2 Adds new capabilities, achieves greater semantic accuracy and gives better support for code generation. Model Driven Architecture Defines a framework for Code Generation. Platform independent model are initially defined and then such models are refined for the particular platform. Profiles Means of tailoring UML for particular purposes. Extensions of the language can be inserted.
Introduction SysML MARTE Code Generation Conclusions and Remarks Target Languages SystemC Represents a flexible choice. SystemC can be used from early design phases down to the implementation phase. Promela Is used for verification through the SPIN Model checker Other Possibilities VHDL, Verilog or similar languages can be used as target languages when HW systems are designed.
Introduction SysML MARTE Code Generation Conclusions and Remarks Target Languages SystemC Represents a flexible choice. SystemC can be used from early design phases down to the implementation phase. Promela Is used for verification through the SPIN Model checker Other Possibilities VHDL, Verilog or similar languages can be used as target languages when HW systems are designed.
Introduction SysML MARTE Code Generation Conclusions and Remarks Target Languages SystemC Represents a flexible choice. SystemC can be used from early design phases down to the implementation phase. Promela Is used for verification through the SPIN Model checker Other Possibilities VHDL, Verilog or similar languages can be used as target languages when HW systems are designed.
Introduction SysML MARTE Code Generation Conclusions and Remarks Code generation from Design Languages Commercial solutions Statemate by I-Logix StateFlow by Mathworks (part of Simulink) Research Efforts Generation of test cases. Behavioral Models. RTL and Synthesizable models UML definition of SystemC model Concerns Expressiveness and Performance
Introduction SysML MARTE Code Generation Conclusions and Remarks Code generation from Design Languages Commercial solutions Statemate by I-Logix StateFlow by Mathworks (part of Simulink) Research Efforts Generation of test cases. Behavioral Models. RTL and Synthesizable models UML definition of SystemC model Concerns Expressiveness and Performance
Introduction SysML MARTE Code Generation Conclusions and Remarks Code generation from Design Languages Commercial solutions Statemate by I-Logix StateFlow by Mathworks (part of Simulink) Research Efforts Generation of test cases. Behavioral Models. RTL and Synthesizable models UML definition of SystemC model Concerns Expressiveness and Performance
Introduction SysML MARTE Code Generation Conclusions and Remarks Outline Introduction 1 SysML 2 MARTE 3 Code Generation 4 5 Conclusions and Remarks
Introduction SysML MARTE Code Generation Conclusions and Remarks SysML Profile Rationale SysML is a graphical modeling language for specifying, analyzing, designing and verifying complex system. Internals SysML contains diagrams that are part of UML2, modified diagrams from UML2 and new diagrams. Scope SysML is particularly adapt for modeling HW/SW systems and aims at extending applicability of UML language to such context.
Introduction SysML MARTE Code Generation Conclusions and Remarks SysML Profile Rationale SysML is a graphical modeling language for specifying, analyzing, designing and verifying complex system. Internals SysML contains diagrams that are part of UML2, modified diagrams from UML2 and new diagrams. Scope SysML is particularly adapt for modeling HW/SW systems and aims at extending applicability of UML language to such context.
Introduction SysML MARTE Code Generation Conclusions and Remarks SysML Profile Rationale SysML is a graphical modeling language for specifying, analyzing, designing and verifying complex system. Internals SysML contains diagrams that are part of UML2, modified diagrams from UML2 and new diagrams. Scope SysML is particularly adapt for modeling HW/SW systems and aims at extending applicability of UML language to such context.
Introduction SysML MARTE Code Generation Conclusions and Remarks SysML Profile
Introduction SysML MARTE Code Generation Conclusions and Remarks Block Definition Diagrams Blocks are basic structural elements used to specify hierarchies and interconnections. BDDs describe the relationships between blocks. bdd System << block >> << block >> SoC1 SoC2 parts module1 module2 <> <> flow ports inout flowPort_3
Introduction SysML MARTE Code Generation Conclusions and Remarks Block Definition Diagrams bdd SoC1_Structure << block >> << block >> SoC1 module1 parts values module1 module1 value_1 module2 flow ports out flowPort_1: type flow ports in flowPort_2: type inout flowPort_3 << block >> module2 values module2 value_2 flow ports in flowPort_1: type out flowPort_2: type inout flowPort_3: type
Introduction SysML MARTE Code Generation Conclusions and Remarks Internal Block Diagrams Describes the internal structure of a block specifying its interconnections. ibd SoC1 flowPort_1 flowPort_3 module1 module2 <> <> flowPort_2
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