Entity declaration mode: in: flow into the circuit out: flow - PDF document

Outline 1. Basic VHDL program Basic Language Constructs of 2. Lexical elements and program format 3. Objects VHDL 4. Data type and operators RTL Hardware Design Chapter 3 1 RTL Hardware Design Chapter 3 2 by P. Chu by P. Chu Design unit • Building blocks in a VHDL program 1. Basic VHDL program • Each design unit is analyzed and stored independently • Types of design unit: – entity declaration – architecture body – package declaration – package body – configuration RTL Hardware Design Chapter 3 3 RTL Hardware Design Chapter 3 4 by P. Chu by P. Chu Entity declaration • mode: – in: flow into the circuit – out: flow out of the circuit • Simplified syntax – inout: bi-directional • E.g. RTL Hardware Design Chapter 3 5 RTL Hardware Design Chapter 3 6 by P. Chu by P. Chu 1

• A common mistake with mode • Fix: use an internal signal RTL Hardware Design Chapter 3 7 RTL Hardware Design Chapter 3 8 by P. Chu by P. Chu Architecture body E.g. • Simplified syntax • An entity declaration can be associated with multiple architecture bodies RTL Hardware Design Chapter 3 9 RTL Hardware Design Chapter 3 10 by P. Chu by P. Chu Other design units VHDL Library • Package declaration/body: • A place to store the analyzed design units – collection of commonly used items, such as • Normally mapped to a directory in host data types, subprograms and components computer • Configuration: • Software define the mapping between the – specify which architecture body is to be bound symbolic library and physical location with the entity declaration • Default library: “work” • Library “ieee” is used for many ieee packages RTL Hardware Design Chapter 3 11 RTL Hardware Design Chapter 3 12 by P. Chu by P. Chu 2

Processing of VHDL code • E.g. • Analysis – Performed on “design unit” basis – Check the syntax and translate the unit into an intermediate form – Store it in a library • Line 1: invoke a library named ieee • Elaboration • Line 2: makes std_logic_1164 package – Bind architecture body with entity visible to the subsequent design units – Substitute the instantiated components with architecture description • The package is normally needed for the – Create a “flattened”' description std_logic/std_logic_vector data type • Execution – Simulation or synthesis RTL Hardware Design Chapter 3 13 RTL Hardware Design Chapter 3 14 by P. Chu by P. Chu Lexical elements • Lexical element: – Basic syntactical units in a VHDL program 2. Lexical elements and • Types of Lexical elements: program format – Comments – Identifiers – Reserved words – Numbers – Characters – Strings RTL Hardware Design Chapter 3 15 RTL Hardware Design Chapter 3 16 by P. Chu by P. Chu Identifier Comments • Starts with - - • Identifier is the name of an object • Just for clarity • Basic rules: • e.g., – Can only contain alphabetic letters, decimal digits and underscore – The first character must be a letter – The last character cannot be an underscore – Two successive underscores are not allowed RTL Hardware Design Chapter 3 17 RTL Hardware Design Chapter 3 18 by P. Chu by P. Chu 3

Reserved words • Valid examples: A10, next_state, NextState, mem_addr_enable • Invalid examples: sig#3, _X10, 7segment, X10_, hi_ _there • VHDL is case insensitive: – Following identifiers are the same: nextstate, NextState, NEXTSTATE, nEXTsTATE RTL Hardware Design Chapter 3 19 RTL Hardware Design Chapter 3 20 by P. Chu by P. Chu Numbers, characters and strings Program format • Number: – Integer: 0, 1234, 98E7 • VHDL is “free-format”: blank space, tab, new-line – Real: 0.0, 1.23456 or 9.87E6 can be freely inserted – Base 2: 2#101101# • e.g., the following are the same • Character: – ‘A’, ‘Z’, ‘1’ • Strings – “Hello”, “101101” • Note – 0 and ‘0’ are different – 2#101101# and “101101” are different RTL Hardware Design Chapter 3 21 RTL Hardware Design Chapter 3 22 by P. Chu by P. Chu • A good “header” RTL Hardware Design Chapter 3 23 RTL Hardware Design Chapter 3 24 by P. Chu by P. Chu 4

Objects • A named item that hold a value of specific data type 3. Objects • Four kinds of objects – Signal – Variable – Constant – File (cannot be synthesized) • Related construct – Alias RTL Hardware Design Chapter 3 25 RTL Hardware Design Chapter 3 26 by P. Chu by P. Chu Signal Variable • Declared in the architecture body's declaration • Declared and used inside a process section • Variable declaration: • Signal declaration: variable variable_name, ... : data_type signal signal_name, signal_name, ... : data_type • Variable assignment: • Signal assignment: variable_name := value_expression; signal_name <= projected_waveform; • Contains no “timing info” (immediate assignment) • Ports in entity declaration are considered as signals • Used as in traditional PL: a “symbolic memory location” where a value can be stored and modified • Can be interpreted as wires or “wires with memory” (i.e., FFs, latches etc.) • No direct hardware counterpart RTL Hardware Design Chapter 3 27 RTL Hardware Design Chapter 3 28 by P. Chu by P. Chu • It is a good idea to avoid “hard literals” Constant • Value cannot be changed • Constant declaration: constant const_name, ... : data_type := value_expression • Used to enhance readability – E.g., RTL Hardware Design Chapter 3 29 RTL Hardware Design Chapter 3 30 by P. Chu by P. Chu 5

Alias 4. Data type and operators • Not a object • Standard VHDL • Alternative name for an object • IEEE1164_std_logic package • Used to enhance readability • IEEE numeric_std package – E.g., RTL Hardware Design Chapter 3 31 RTL Hardware Design Chapter 3 32 by P. Chu by P. Chu Data type Data types in standard VHDL • Definition of data type • integer: – A set of values that an object can assume. – Minimal range: -(2^31-1) to 2^31-1 – A set of operations that can be performed on – Two subtypes: natural, positive objects of this data type. • boolean: (false, true) • VHDL is a strongly-typed language • bit: ('0', '1') – an object can only be assigned with a value of – Not capable enough its type • bit_vector: a one-dimensional array of bit – only the operations defined with the data type can be performed on the object RTL Hardware Design Chapter 3 33 RTL Hardware Design Chapter 3 34 by P. Chu by P. Chu Operators in standard VHDL RTL Hardware Design Chapter 3 35 RTL Hardware Design Chapter 3 36 by P. Chu by P. Chu 6

• std_logic_vector IEEE std_logic_1164 package – an array of elements with std_logic data type • What’s wrong with bit? – Imply a bus • New data type: std_logic, std_logic_vector – E.g., signal a: std_logic_vector(7 downto 0); • std_logic : – Another form (less desired) – 9 values: ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') signal a: std_logic_vector(0 to 7); • '0', '1': forcing logic 0' and forcing logic 1 • 'Z': high-impedance, as in a tri-state buffer. • Need to invoke package to use the data type: • 'L' , 'H': weak logic 0 and weak logic 1, as in wired- library ieee; logic use ieee.std_logic_1164. all ; • 'X', 'W': “unknown” and “weak unknown” • 'U': for uninitialized • '-': don't-care. RTL Hardware Design Chapter 3 37 RTL Hardware Design Chapter 3 38 by P. Chu by P. Chu Overloaded operator IEEE std_logic_1164 package • Which standard VHDL operators can be applied to • Type conversion function in std_logic_1164 std_logic and std_logic_vector? package: • Overloading: same operator of different data types • Overloaded operators in std_logic_1164 package RTL Hardware Design Chapter 3 39 RTL Hardware Design Chapter 3 40 by P. Chu by P. Chu • E.g., Operators over an array data type • Relational operators for array – operands must have the same element type but their lengths may differ – Two arrays are compared element by element, form the left most element – All following returns true • "011"="011", "011">"010", "011">"00010", "0110">"011" RTL Hardware Design Chapter 3 41 RTL Hardware Design Chapter 3 42 by P. Chu by P. Chu 7