Embedded analy+cs delivers system-wide visibility for debug, safety, - PowerPoint PPT Presentation

Embedded analy+cs delivers system-wide visibility for debug, safety, security and more... Design and Reuse IP-SoC Days – Shanghai 2017

Agenda • Some obvious statements • Some problems with exis4ng approaches • Key requirements • The UltraSoC approach • Some examples of performance analysis and debug • Use cases • Summary 21 September 2017

Some obvious statements SoCs have become increasingly complicated & are not going to get simpler • • Contain several processors, from different vendors • Verified in isola4on and come with test suite • Contain 100s of IP blocks • Each verified in isola4on • Contain complex interconnects • Verified for certain, iden4fied condi4ons • SoLware created by large disparate teams • If lucky, modules and subsystem verified for certain, iden4fied condi4ons. • All this has to successfully work together Understanding real world system behaviour is HARD! • 21 September 2017

Some problems with exis+ng approaches Processor-centric, not system-centric • • Processors are a very small part of the overall system It’s very difficult to monitor: • • Bus behaviour, memory controllers, interac4ons between blocks There is very liXle analy4cs • • Just extrac4ng raw data Intrusive • Ad hoc • Developing, but s4ll essen4ally signal-based • • Hard to close 4ming In-field monitoring is not easy • 21 September 2017

Key requirements • A system-centric vendor-neutral debug and monitoring infrastructure • One that enables access to different proprietary debug schemes • Enables monitoring of interconnect, interfaces and custom logic • Run-4me configurable • Re-use the hardware to provide visibility for different scenarios • Run-4me configura4on of cross-triggering • Support 10s if not 100s of cross-triggering events • These can be interrogated aLer a problem to determine actual status • Need to be power aware • Built-in security • Can be used during the whole development flow and in the field 21 September 2017

UltraSoC embedded analy+cs architecture System modules and System interconnect interconnect CPU Custom logic 1. Protocol-aware 2. Op4mized message- analysis modules with Downstream passing infrastructure Analytic Analytic Analytic Upstream “smart” filters and trace module module module Message infrastructure 3. Communicators. Eg: USB, JTAG, streaming, Communicator Communicator on-chip 4. Visualiza4on soLware SoC boundary External External debugger software API 21 September 2017

How does it work? • Protocol-aware analysis modules • Processors: ARM, MIPS, Ceva, RISC-V, + more System interconnect • Buses: AXi, CHI, Netspeed, + more CPU Custom logic • Filter, match, trigger, store, output Downstream Analytic Analytic Analytic • Analysis done in hardware, on-chip Upstream module module module • Reduces need for high-speed off-chip transport Message infrastructure • Can be used in-system and in-field Communicator Communicator SoC boundary • A choice of communicators External External debugger software API • To suite system requirements 21 September 2017

Example problems UltraSoC analy+cs solves UltraSoC IP Status Status mon mon Radio IF Radio IF DSP Why is the CPU FFT I I I$ I$ TCM TCM not performing as What is the Processor Processor Interconnect D D D$ D$ fast as expected? TCM TCM mismatch Status Status between the USB Turbo mon mon MAC DSP DSP Interconnect Debug host & the Hub Status Status DSP? mon mon Bus mon Why do some DMA UltraSoC Peripheral Interconnect Infrastructure transfers take too long? Status mon DMA-1 RAM DMA-2 Timer Security Why does the Interconnect What is going on Bus mon system hang with my memory or deadlock Status PHY mon DFI-PHY DRAM controller controller? on rare occasions? DDR3 21 September 2017

Example 1: “Where have my MIPS gone?” UltraSoC IP Status Status mon mon Radio IF Radio IF DSP Why is the CPU FFT I I I$ I$ TCM TCM not performing as Processor Processor D D Interconnect D$ D$ TCM TCM fast as expected? Status Status USB Turbo mon mon MAC DSP DSP Interconnect Debug Hub Status Status mon mon Bus mon UltraSoC UltraSoC Peripheral Interconnect Infrastructure Infrastructure Status mon SM DMA-1 RAM DMA-2 Timer Security Interconnect Bus mon Status PHY mon DFI-PHY DRAM controller DDR3 21 September 2017

Example 1: “Where have my MIPS gone?” UltraSoC IP Status Status mon mon Radio IF Radio IF DSP Why is the CPU FFT I I I$ I$ TCM TCM not performing as Processor Processor D D Interconnect D$ D$ TCM TCM fast as expected? CPU spent cycles Status Status USB Turbo mon mon MAC DSP DSP Interconnect Debug Hub Status Status mon mon Bus mon 8% 12% Compute UltraSoC UltraSoC Peripheral Interconnect Infrastructure Infrastructure Stall 1 outstanding Status mon SM DMA-1 RAM DMA-2 Timer Security 80% Stall 2 outstanding Interconnect Bus mon Status PHY mon DFI-PHY DRAM controller DDR3 21 September 2017

Example 2: DDR bandwidth UltraSoC IP Status Status mon mon Radio IF Radio IF DSP FFT I I I$ I$ TCM TCM Processor Processor D D Interconnect D$ D$ TCM TCM Status Status SM USB Turbo mon mon MAC DSP DSP Interconnect Debug Hub Status Status mon mon Bus mon Why do some DMA UltraSoC Peripheral Interconnect Infrastructure transfers take too long? Status mon DMA-1 RAM DMA-2 Timer Security Interconnect Bus mon What is going on with my memory SM Status PHY mon DFI-PHY DRAM controller controller? DDR3 21 September 2017

Example 2: DDR bandwidth UltraSoC IP Status Status mon mon Radio IF Radio IF DSP FFT I I I$ I$ TCM TCM Windowed DDR traffic Processor Processor D D Interconnect D$ D$ TCM TCM 1.00E+09 Status Effec4ve B/s Status SM USB Turbo mon mon MAC DSP DSP 5.00E+08 Interconnect Debug Hub Status Status 0.00E+00 mon mon Bus mon Why do some 1000 4000 7000 10000 13000 16000 19000 22000 25000 28000 31000 34000 37000 40000 43000 46000 49000 DMA UltraSoC Peripheral Interconnect Infrastructure Time in ns transfers take too long? Status mon DMA-1 RAM DMA-2 Timer Security DSP1 DSP2 CPU1 CPU2 Interconnect Look at I$ from compute engines • Bus mon What is going on Aggregate bandwidth from each is within spec • with my memory SM Status PHY mon DFI-PHY DRAM controller But at Time 2300 Combined peak I$ read request of controller? • >2GB/s, cf average of ~570MBs DDR3 21 September 2017

Cross-triggering 1. If write to an address System interconnect range occurs, send event A 2. Configure to store CPU Custom logic 3. Write detected. Event trace in ring buffer. Stop A broadcast to all & output on event A modules in chip Downstream Analytic Analytic Analytic Upstream module module module 4. Event A received. Output trace Message infrastructure Communicator Communicator 5. Trace data displayed SoC boundary External External debugger software API 21 September 2017

The importance of cross-triggering • Gigabytes of trace data can be reduced to kilobytes AID ADATA AID ADATA • In-field, events that only AID ADATA occur once a week can be ATB Samples AID ADATA AID ADATA captured and uploaded Only capture AID ADATA data of interest AID ADATA • Cross-trigger events can be AID ADATA AID ADATA AID ADATA sourced from anywhere, AID ADATA AID ADATA even hardware signals ADATA ADATA AID AID ADATA AID ADATA AID • Run-4me selec4on is Without Cross- With Cross- essen4al Triggering Triggering 21 September 2017

Use case 1: classic debug 21 September 2017

Use case 2: in-field debugging and analysis • Find the cause of rate problems • Monitor ongoing performance • Fix problems through upgrades • Input to next-genera4on SoC 21 September 2017

Use-case 3: bare metal security and safety 21 September 2017

Summary • In complex SoCs • Embedded analy4cs is essen4al • A unified approach can save months of effort and a lot of money • Embedded analy4cs hardware can be used for • Classic lab debug • In field problem solving • Life4me analysis • A separate domain to enhance security and safety 21 September 2017