Announcements EECS 373 • Homework #2 Design of Microprocessor-Based Systems • Where was I last week? – VLCS’14 – MobiCom’14 – HotWireless’14 Prabal Dutta University of Michigan Lecture 5: Memory and Peripheral Busses September 16, 2014 1 2 Emerging Retail Environment: A Walled Garden Visible Light Communications and Positioning • Often have line-of-sight to lighting $" $ 01100101000 � +))))))), – Groceries � ( ( % &'! � % &) *) ( ( % &'$ � – Drugstores � ( ( % &'$ % &'# ! � " !" � � % &'# % &'! #" – Megastores # ! Illuminate Idle TX <66> TX packet Smart Phone LED Luminaire Captured using a rolling shutter – Hardware stores f 4 – Enterprise settings • Lots of overhead lighting in retail S4 • Retailers deploying LED lighting f 3 • Customers using phones in stores S3 – Surf, Scan, Share f 2 S4 Image processing extracts beacon locations and frequencies • Customers installing retailer apps S2 S3 – Maps, Barcodes, Deals, Shopping t e u f 1 m p S2 o C S1 S1 e i z m i i n M 3 4 Outline Harmonia Tag • Announcements • Review • ARM AHB-Lite -10.0 Carrier UWB Mask -20.0 Amplitude (dBm) -30.0 -40.0 -50.0 -60.0 5.4e+09 5.6e+09 5.8e+09 6e+09 6.2e+09 Frequency (Hz) 5 6
What happens after a power-on-reset (POR)? System Memory Map • On the ARM Cortex-M3 !.equ !STACK_TOP,!0x20000800! !.text! • SP and PC are loaded from !.syntax !unified! !.thumb! the code (.text) segment !.global !_start! !.type !start,!%function! • Initial stack pointer ! _start:! – LOC: 0x00000000 !.word !STACK_TOP,!start! – POR: SP ! mem(0x00000000) start:! !movs!r0,!#10! • Interrupt vector table !...! – Initial base: 0x00000004 – Vector table is relocatable – Entries: 32-bit values – Each entry is an address – Entry #1: reset vector • LOC: 0x0000004 • POR: PC ! mem(0x00000004) • Execution begins 7 Accessing memory locations from C Some useful C keywords • Memory has an address and value • const • Can equate a pointer to desired address – Makes variable value or pointer parameter unmodifiable – const foo = 32; • Can set/get de-referenced value to change memory • register – Tells compiler to locate variables in a CPU register if possible – register int x; • static !#define!!SYSREG_SOFT_RST_CR!!0xE0042030! ! – Preserve variable value after its scope ends !uint32_t!*reg!=!(uint32_t!*)(SYSREG_SOFT_RST_CR);! – Does not go on the stack ! !main!()!{! – static int x; !!!*reg!|=!0x00004000;!//!Reset!GPIO!hardware! • volatile !!!*reg!&=!~(0x00004000);! !}! – Opposite of const ! ! – Can be changed in the background – volatile int I; 9 10 What happens when this � instruction � executes? � *reg += 3 � is turned into a ld, add, str sequence • Load instruction – A bus read operation commences – The CPU drives the address � reg � onto the address bus #include!<stdio.h>! – The CPU indicated a read operation is in process (e.g. R/W#) #include!<inttypes.h>! – Some � handshaking � occurs ! #define!REG_FOO!0x40000140! – The target drives the contents of � reg � onto the data lines ! – The contents of � reg � is loaded into a CPU register (e.g. r0) main!()!{! • Add instruction !!uint32_t!*reg!=!(uint32_t!*)(REG_FOO);! – An immediate add (e.g. add r0, #3) adds three to this value !!*reg!+=!3;! • Store instruction ! – A bus write operation commences !!printf( � 0x%x\n � ,!*reg);!//!Prints!out!new!value! – The CPU drives the address � reg � onto the address bus }! – The CPU indicated a write operation is in process (e.g. R/W#) – Some � handshaking � occurs – The CPU drives the contents of � r0 � onto the data lines – The target stores the data value into address � reg � 11 12
Modern embedded systems have multiple busses Why have so many busses? • Many designs considerations Atmel SAM3U – Master vs Slave – Internal vs External – Bridged vs Flat – Memory vs Peripheral – Synchronous vs Asynchronous Expanded – High-speed vs low-speed 373 focus – Serial vs Parallel – Single master vs multi master – Single layer vs multi layer – Multiplexed A/D vs demultiplexed A/D • Discussion: what are some of the tradeoffs? Historical 373 focus 13 14 APB APB signal definitions • IDLE • PCLK: the bus clock source (rising-edge triggered) – Default APB state • PRESETn: the bus (and typically system) reset signal (active low) • SETUP • PADDR: the APB address bus (can be up to 32-bits wide) – When transfer required • PSELx: the select line for each slave device – PSELx is asserted Setup phase begins • PENABLE: indicates the 2 nd and subsequent cycles of an APB xfer with this rising edge – Only one cycle • PWRITE: indicates transfer direction (Write=H, Read=L) • ACCESS • PWDATA: the write data bus (can be up to 32-bits wide) – PENABLE is asserted • PREADY: used to extend a transfer – Addr, write, select, and • PRDATA: the read data bus (can be up to 32-bits wide) write data remain stable • PSLVERR: indicates a transfer error (OKAY=L, ERROR=H) – Stay if PREADY = L – Goto IDLE if PREADY = H and no more data – Goto SETUP is PREADY = H and more data pending Setup Access Phase Phase 15 16 Let’s say we want a device that provides data from Device provides data from switch A if address a switch on a read to any address it is assigned. 0x00001000 is read from. B if address 0x00001004 (so returns a 0 or 1) is read from ! PREADY ! PREADY ! ! PRDATA[32:0] PRDATA[32:0] PWRITE ! ! PWRITE ! ! ! ! PENABLE ! PENABLE ! Mr. Mr. ! ! Switch Switch PSEL ! PSEL ! Mrs. ! ! Switch PADDR[7:0] ! PADDR[7:0] ! ! ! PCLK ! PCLK ! ! ! ! ! 17 18
All reads read from register, all writes write… Outline • Announcements PWDATA[31:0] ! PREADY ! ! PRDATA[32:0] PWRITE ! ! • Review ! ! 328bit!Reg ! ! PENABLE ! D[31:0]!!!!!!!!!!!!!!!!!!! ! ! • ARM AHB-Lite ! ! !!!!!!!!!!!!!!!!!!Q[31:0]! EN! PSEL ! ! !! ! !!!!C!!!!!!!!!!!!!!!! ! ! PADDR[7:0] ! ! ! PCLK ! ! ! PREADY ! ! ! We are assuming APB only gets lowest 8 bits of address here… 19 20 Actel SmartFusion system/bus architecture Advanced Microcontroller Bus Architecture (AMBA) - Advanced High-performance Bus (AHB) - Advanced Peripheral Bus (APB) AHB APB • High performance • Low power • Pipelined operation • Latched address/control • Burst transfers • Simple interface • Multiple bus masters • Suitable of many peripherals • Split transactions 21 22 AHB-Lite supports single bus master AHB-Lite bus master/slave interface and provides high-bandwidth operation • Global signals – HCLK • Burst transfers – HRESETn • Master out/slave in – HADDR (address) • Single clock-edge – HWDATA (write data) operation – Control • HWRITE • HSIZE • Non-tri-state • HBURST implementation • HPROT • HTRANS • HMASTLOCK • Configurable bus width • Slave out/master in – HRDATA (read data) – HREADY – HRESP 23 24
AHB-Lite signal definitions Key to timing diagram conventions • Global signals – HCLK: the bus clock source (rising-edge triggered) • Timing diagrams – HRESETn: the bus (and system) reset signal (active low) – Clock • Master out/slave in – HADDR[31:0]: the 32-bit system address bus – Stable values – HWDATA[31:0]: the system write data bus – Transitions – Control – High-impedance • HWRITE: indicates transfer direction (Write=1, Read=0) • HSIZE[2:0]: indicates size of transfer (byte, halfword, or word) • HBURST[2:0]: indicates single or burst transfer (1, 4, 8, 16 beats) • Signal conventions • HPROT[3:0]: provides protection information (e.g. I or D; user or handler) – Lower case � n � denote • HTRANS: indicates current transfer type (e.g. idle, busy, nonseq, seq) active low (e.g. RESETn) • HMASTLOCK: indicates a locked (atomic) transfer sequence • Slave out/master in – Prefix � H � denotes AHB – HRDATA[31:0]: the slave read data bus – Prefix � P � denotes APB – HREADY: indicates previous transfer is complete – HRESP: the transfer response (OKAY=0, ERROR=1) 25 26 Basic read and write transfers with no wait states Read transfer with two wait states Pipelined Address & Data Transfer Valid data Two wait states produced added by slave by asserting HREADY low 27 28 Write transfer with one wait state Wait states extend the address phase of next transfer Address stage of the next transfer is also extended One wait state Valid data One wait state added by slave held stable added by slave by asserting by asserting HREADY low HREADY low 29 30
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