DUNE DAQ Data format inside FPGA David Cussans 14 th June 2018

Introduction • Format for data inside FPGAs • Part of definition of processing blocks. • Want to run logic ~ 100MHz – 400MHz • Reuse gates multiple times in single 2MHz ADC sample time. • Aim to be able to stream data ( pipelined logic ) where possible • Rather than read in block, process, transmit • à Probably (?) implies time-wise ordered data ( sample 1,2,3,4…) , rather than channel-wise data ( channel 1,2,3,…. ) • … but do want some block structure, for transmission to event builder and , e.g. ease of recovery from lost data. David Cussans | DAQ Hardware meeting, 14 th June 18 2

Hardware Layout • Look at: • Combiner/splitter à compression interface • Compression à Buffer controller interface Diagram – Babak Abi To Back- end Trigger Command Data Selection David Cussans | DAQ Hardware meeting, 14 th June 18

Assumed parameters • 4 FPGAs per APA • à 2560 / 4 = 640 wires per APA • 2MSample/s , 12-bits • Aim for < 400MHz clock for logic processing • Try ~ 320MHz processing clock • à Width of “data bus” = 12 x f sample x N chan / f clock = 48 • Assume Fibonacci (or some other) encoding(compression) of sample differences. • N.B. This is a “straw person” aimed to provoke comment, not the final word…. David Cussans | DAQ Hardware meeting, 14 th June 18 4

Conventions • S ij = 12-bit Single Phase TPC sample from channel “i” at clock cycle “j” within a block of data • For compressed data: • Ped i = sample value for channel “i” at start of block of data • D ij = encoded data for channel “i” , clock cycle “j” • Possibly not DUNE official nomenclature Channel Number ➡ ️ S 1,1 S 2,1 S 3,1 S 4,1 … … … S i,1 S 1,2 S 2,2 S 3,2 S 4,2 … … … S i,2 S 1,3 S 2,3 S 3,3 S 4,3 … … … S i,3 Sample Number ⬇ ️ . . . . . . . . . . . . . . . . . . . . . . . . S 1,j S 2,j S 3,j S 4,j … … … S i,j David Cussans | DAQ Hardware meeting, 14 th June 18 5

Raw Data Format David Cussans | DAQ Hardware meeting, 14 th June 18 6

Compressed ← 48 bits → Timestamp Block #N Data Format Additional headers Ped 1 Ped 2 Ped 3 Ped 4 ← 160 clock cycles → Pedestals for block Ped 5 Ped 6 Ped 7 Ped 8 . . . Ped 637 Ped 638 Ped 639 Ped 640 Compressed D1,1, D2,1, .. ← variable → deltas, #1 . . .. , D639,1, D640,1, padding checksum Compressed D1,2, D2,2, .. deltas, #2 . . .. , D639,2, D640,2, padding checksum . . ……… . . Compressed D1,N, D2,N, .. deltas, #N . . .. , D639,N, D640,N, padding checksum Additional checksum , Nsamples David Cussans | DAQ Hardware meeting, 14 th June 18 7

Conclusion • Need to define interfaces as part of task of defining processing blocks. • For internal data paths, define a format optimized for FPGAs • Allow for maximum reuse of logic on multiple clock cycles • Minimize the amount of storage needed for intermediate results. • There will also be additional control lines • E.g. Data-valid strobes • Run logic ~ 350MHz to allow for headers • Don’t need an exact multiple of sample frequency – have strobes. David Cussans | DAQ Hardware meeting, 14 th June 18 8

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DUNE DAQ Data format inside FPGA David Cussans 14 th June 2018 Introduction Format for data inside FPGAs Part of definition of processing blocks. Want to run logic ~ 100MHz 400MHz Reuse gates multiple times in single

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