Development of high rate MWPC and data compression function with - PowerPoint PPT Presentation

Development of high rate MWPC and data compression function with FADC (II) Nguyen Minh Truong (Osaka U.), Coworker: Masaharu Aoki(Osaka U.), Youichi Igarashi(KEK), Masatoshi Saito(KEK), Hiroaki Natori (KEK), Nguyen Duy Thong (Osaka U.) Open-It, Nov. 20 th , 2014, at J-PARC 1 1

Contents ● Motivation ● FADC readout board + Original firmware design + New firmware design ● Test new firmware design ● Summary 2

Motivation ● MWPC will be used to take signal from DeeMe experiment Delay signal Raw wave form wave form after subtracting baseline Signal of MWPC in the beam test with e- beam at KURRI, Aug 2014 We want to see delay signal but the base line is not flats => should use FADC board to readout signal 3

Motivation ● In order to monitor beam off timing background, we want to read out data with time length as much as possible (~ 80 micro second) Recode time length as long as possible 4

Original Readout FADC board 10-bits 100-MHz FADC system developed by IGARASHI Youichi for TREK experiment Input channel Input channel SiTCP 100Mbps 16 FADC Spartan 6 (AD9216 100MHz) 2input and 2output/ 1fadc - Data speed transfer is 20 events/ s → dead time ~ 50ms + 32 channels/event 5 + 8192 sample points /channel

Dead Time Of Original Firmware (with 8192 sample point) 600ns 10us 70us background ●●● ●●● Record data region main pulse Beam trigger 40ms Cosmic ray trigger ●●● { Busy signal ~50ms Original firmware data Data Requirement { <20ms Busy signal Data data data data data time 6

Original Readout FADC board Data SiTCP bandwidth (100Mbps) First Data method SiTCP bandwidth (1Gbps) Second method Data SiTCP bandwidth (100Mbps) ● To monitor cosmic rays background, the dead time of readout board should small than 20ms but original firmware have dead time ~50ms Data before compress => compression ratio = > 2.5 7 Data after compress

New design for FADC board ● Fast data transfer → dead time < 20ms ● Moulder design +Extensibility → User can easy modify for their experiment +Easy for debug ● Multiple trigger: +External trigger +Self trigger ● Have slow control to control number of sample points, number of channels, threshold, … ● Time stamp and Event tag to synchronize multiple FADC readout board 8

Data format of FADC Readout board Word Event Format 0xFAFA Begin of Event Byte oder, 0xF1F2 = Big Endian, 0xF1F2 0xF2F1 = Little Endian Word Channel Format 0xA1A1 Trigger type: 0xFFFC Start of Channel Data Block or 0xA1A1 = External trigger 0xFC01 Module ID 0xB1B1 0xB1B1 = Self trigger 10l 14 a 7 = Header Format Version Code, 10a 7 b 7 10m 14 l 14 m 14 n 14 = Bit-Mask of Active channels b 7 = Firmware Version Code 10n 14 c 14 = Module ID, lower 14-bits of 10c 14 Start of channel module's IP address 0xFFq 8 q 8 = channel number Comp. 10d 14 d 14 e 14 = Local Event Number,total format Compressor data format 28bits 10e 14 0xFDFD End of Channel 10f 9 g 5 f 9 = reserved, g 9 = Event tag Start of channel 0xFFq 8 q 8 = channel number 10h 14 Comp. Compressor data format 10i 14 format h 14 i 14 j 14 k 14 = Local Time stamp, 0xFDFD End of Channe l total 56 bits 10j 14 ●●● ●●● 10k 14 Channel data format 0xFFFD End of Channel Data Block 0xFBFB End of Event Data 9

Data format of compressor Begin of Compressor 0xFEFE Field size (raw data) 0 0 0 0 Raw next 1 Raw data x x x x x x x x x x Raw data next 1 Raw data x x x x x x x x x x End raw data 0 Field size(3-bits delta) 0 0 1 1 3-bits delta x x x 3-bits delta x x x ●●● ●●● ●●● ●●● End of 3-bits delta 1 0 0 Field size(n-bits delta) n n n n n-bits delta x x x x ●●● x ● ●● x x x x ●●● x End of n bits delta 1 0 0 0 ●●● 0 End of delta 1 1 1 1 compressor stream End of Compressor 0xFEFD 10

New design for FADC board 25MHz 100MHz HIT_FLAGS REG VME-bus CH-FORMATTER SENDER [ALIVE_CH] FRONTEND 32 7 TCP_FULL ICH_FLAGS 32 32 LATCH TAG_LATCH TCP_OPEN DATA[9:0] DATA processor eFiFo 7 DATA[9:0] ODATA eFiFo EVN- [7:0] FORMATTER MUX ● ● DATA[9:0] IDATA ● ● [9:0] SiTCP IDATA IDATA IDATA ODATA ODATA ODATA ● ● [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] DATA[9:0] (100Mbps) eFiFo IBUSY OBUSY IBUSY OBUSY TCP_TX IBUSY OBUSY IREQ OREQ IREQ OREQ _WR 6 OACK IACK OACK IACK OVD IVD OVD IVD OVD IVD WE RE HIT_LATCH CH IBUSY OBUSY OACK IACK IREQ OREQ MUX Control OACK IACK IREQ OACK OVD IVD CHSEL 6 CHSEL 64 TIME_STAMP FROTEND_MODE _LATCH EVENT_READ_BUSY TRIGGER TRIGGER MANAGER PC EVENT_READ OBUSY 64 EVENT_TIME RESET CLOCK_ COUNTER 11

Delta compression algorithm Delta ∆ ADC = ADC n+1 - ADC n +Calculate delta +Calculate delta average of some sample point +Decide how many bits to use for delta code ∆ 2 = 0 ∆ 1 ∆ 3 ∆ 5 ∆ 4 = 0 -original data: 548 549 549 547 547 549 12 -delta compression data: 548 549 549 -2 0 2

Compressor module IDATA IDATA: 00000000001 00000000010 00000000011 10 Deltacoder Delta data 00000000001 00000000001 00000000001 NBITS 0000 0011 0011 NBITS 4 10 Delta data Encoder data Encoder 0000-1-0000000001-0..0 0-0011-001-0..0 001-0..0 00011 NBITS 01111 01000 NBITS 5 32 Encoder data Packer data Packer 0 0-0011-001-001 0 0000-1-0000000001 16 13 Output data

Deltacoder Block Diagram IDATA (ex: 0000000010) 10 LATCH 500 501 501 503 10 data_previous (ex: 00000000001) 10 200 10 0 Subtract (ex: 00000000001) Delta_size control 11 switch Output data control 10 4 ODATA (delta/raw data) (ex: 0000000001) 14 ONBITS

Encoder Block Diagram INBITS MASK (ex: 0011) LUT IDATA IDATA 4 (ex: 0000000001) (ex: 0000000001) 10 4 10 LATCH Header field 4 LUT Mask (ex: 0000000111) NBITS_old (ex: 0000) 0 and 4 Shifter 32 No. of 0.. ..0 bits shift 0000000001 5 00.. ..00 0.. ..0 0000000001 16 Header 0 5 (ex: 0-0011-0..0) 16 16 ONBITS 32 0-0011-0..0 0.. ..0 (ex: 0111) 32 OR ODATA 15 32 (ex: 0-0011-001-0..0)

Packer Block Diagram 0 Encoder_data INBITS (ex: 001 – 010-0...0) 5 32 32 Shifter 001-010-0.. ...0 0... ...00 No. of bits 5 data_previous Control ex (001110010111- 0...0) No. of 0.. ..0 001-010-0.. .. 0 0 ..0 bits shift 64 64 OR Output process 64 001110010111001-010-0.. ..0 0 49 15 6 15 64 010-0.. ..0 0.. ..0 0 Output control switch 64 0 001110010111001 16 ODATA 16

Test list of compression module ● Test with counter signal → no loss any sample points during data transfer ● Square signal and pulse signal → FADC readout board can read signal with different delta size ● Delta size change in fly → FADC readout board still work well with delta size changing and different noise level ● DeeMe estimate signal → how much we can compress 17

Test list of compression module Counter signal ( signal will increase or reduce one by one at positive clock) ● Output from readout board Input signal 18

Test compressor module Delta size change in fly ● Different noise level Compression ratio = 2.9 DeeMe estimate signal ● 19

Summary ● We design new firmware for FADC readout board which satisfy for DeeMe project ● Apply delta compression algorithm to compress data +Achieved compression ration is 2.9 + Busy signal with 8192 sample point and 32 channel ~ 18ms ~50ms Busy signal ~18ms New Busy signal +Test compressor module with some edge condition and get good result 20

Thanks for your attention

Backup slides

New design for FADC board Handshake protocol between module A and module B REQ OREQ IREQ ACK +User can modify their own data processor OACK IACK Module A Module B VD IVD +Transfer data in one clock OVD BUSY IBUSY OBUSY DATA ODATA IDATA CLK REQ ACK VD BUSY data1 data2 data3 data4 data5 DATA

Deltacoder Block Diagram Logbase2 REG LUT Delta_size control chunk_size 10 data_previous 10 chunk_counter Logbase2 10 No. of + - bits shift 5 Subtracter Shifter 11 delta_register delta_register1 Deltta_size LUT delta_average Output data control + - Max_delta delta_size

Packer Block Diagram INBITS 5 5 nbits_counts No. of 15 bits shift 6 + - 6 Output control

Packer block diagram 0 15

Overload input signal