Design of a Flexible Open Platform for High Performance Active Networks Sumi Choi, Dan Decasper, John Dehart, Ralph Keller, John Lockwood, Jonathan Turner ,Tilman Wolf Washington University Applied Research Lab http://www.arl.wustl.edu/arl/ Washington Jonathan Turner - 10/25/99 1 WASHINGTON UNIVERSITY IN ST LOUIS
Motivation G Technology advances adding new functionality to internet routers. » logic capabilities growing much faster than IO » packet classification, per flow queueing becoming common » single chip packet processing engines with 16 processors now becoming available G Application-specific processing in routers could become routine. » active networking is one way to exploit trend » alternative model –signalling and resource reservation –packet classification and flow-specific routing G Key challenge is application software . G Need better experimental platforms for researchers. Washington Jonathan Turner - 9/22/99 2 WASHINGTON UNIVERSITY IN ST LOUIS
Towards an Open Internet Router G Modular components. » ability to swap components - both hardware and software – routing, signalling, management software – address lookup and packet classification – queueing and packet scheduling » open, documented and straightforward interfaces G Dynamic insertion of application-specific processing. » active networking model and others G High performance. » gigabit links and scalability to large numbers of ports » packet processing rates of at least a million/ second per link » application-specific processing on large fraction of traffic » need credible demonstrations to influence commercial practice Washington Jonathan Turner - 9/22/99 3 WASHINGTON UNIVERSITY IN ST LOUIS
Active Router Hardware CP AN Processing Element Control Processor 32-64 LCs ANPEs IPPs OPPs ANPEs LCs •global coordination & control Pentium MB NB •routing & signalling protocols Cache Sys. •build routing tables and other FPGA information needed by SPCs APIC •first level code server •reprogrammable for active processing Switch Input Port Processor VCI VCI OUT Washington Jonathan Turner - 9/22/99 4 WASHINGTON UNIVERSITY IN ST LOUIS
Cell Processing CP LCs ANPEs IPPs OPPs ANPEs LCs 3 Switch 4 6 4 Washington Jonathan Turner - 9/22/99 5 WASHINGTON UNIVERSITY IN ST LOUIS
Packet Processing CP LCs ANPEs IPPs OPPs ANPEs LCs 9 9 9 Pentium NB 2 6 Cache Sys. FPGA Switch 2 6 APIC 2 6 Pentium NB Cache Sys. 9 9 9 FPGA APIC Washington Jonathan Turner - 9/22/99 6 WASHINGTON UNIVERSITY IN ST LOUIS
Principal Data Flows Through PE Kernel Packet + Packet IPv4/6 Flow Id Plain Packets IP Packets Classification Header and Routing Processing Kernel Plugins Active Packets . . . Driver Scheduler Active Packet Driver Function Dispatcher . . . . . . SAPF Packet . . . Selector/ Dispatcher . . . . . . Resource Controller G Std. proc. for “ plain” IP packets. » classification & routing, header processing, output queueing G Active packets move through configured kernel plugins. » active function dispatcher passes packets to instances of plugin objects » instantiates objects or triggers download of plugin class, as needed » streamlined processing of SAPF packets using pre-established state Washington Jonathan Turner - 9/22/99 7 WASHINGTON UNIVERSITY IN ST LOUIS
System Level Software Organization Control Processor Policy Plugin Key Rules Plugin DB DB Active ANTS Routing & Code DB Requestor Signalling Java Plugin DB Policy Security VM Controller Controller Gateway ANN Code Code anetd Manager Server Active Plugin Loader Server Kernel Switch Fabric Security Security Plugin Plugin & Policy & Policy Processing Elements Requestor Requestor Controller Controller Active Plugin Loader Active Plugin Loader . . . Kernel Kernel Washington Jonathan Turner - 9/22/99 8 WASHINGTON UNIVERSITY IN ST LOUIS
Physical Configuration Fiber jumper to front panel Transmission Optoelectronics Coder & Decoder Processor Module APIC System FPGA Connectors I O O SE I Main Circuit I O SE Board O I I SE O O I SE I O O I Washington Jonathan Turner - 9/22/99 9 WASHINGTON UNIVERSITY IN ST LOUIS
Field Programmable Port Extender Field Programmable Port Extender G Stackable port card 64 SRAM 32 SDRAM Reprogrammable (1 MB) (32 MB) » can be combined with PE App. Device G Programmable hardware SRAM 32 64 SDRAM (250Kg+100Kb) 100 MHz (1 MB) 100 MHz » FPGA technology (32 MB) » flexible memory config. » change on-the-fly 6.4 Gb/s Utopia Interface Utopia Interface G Reprogrammable ( 3.2 Gb/s ) ( 3.2 Gb/s ) Application Device (RAD) Network Line PE » fully reprogrammable Card Interface Device » four separate memory interfaces G Variety of applications » memory bw: 2.4GB/ s » address lookup & packet class. G Network Interface Device » per flow queueing (NID) » traffic management » relatively static » adapt for different line cards » hardware plugins Washington Jonathan Turner - 9/22/99 10 WASHINGTON UNIVERSITY IN ST LOUIS
Conclusions G High performance active networking need not be an oxymoron. » scalable systems with gigabit links and terabit throughputs are possible with current/ near-term technology » on-going technology improvements will make AN economically viable G Need to focus on active application development. G Need better abstractions, tools, APIs for developers. G Effective & open experimental platforms are essential. » provide realistic testbed » provide more convincing demonstrations » enable system researchers and developers to build on each others efforts Washington Jonathan Turner - 9/22/99 11 WASHINGTON UNIVERSITY IN ST LOUIS
Credits Ralph Keller Sumi Choi John Lockwood John Dehart Tilman Wolf Dan Decasper Washington Jonathan Turner - 9/22/99 12 WASHINGTON UNIVERSITY IN ST LOUIS
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