Design Challenges in High Performance Three ‐ Dimensional Circuits Prof. Eby G. Friedman University of Rochester www.ece.rochester.edu/~friedman January 15, 2010 D43D : System Design for 3D Silicon Integration Workshop 2
An Increasing Interest in 3 ‐ D ICs • Source: IEEEXplore 3 Presentation Outline • Three ‐ dimensional (3 ‐ D) integration • MIT Lincoln Laboratories 3 ‐ D Technology • Physical design issues in 3 ‐ D integration • 3 ‐ D networks ‐ on ‐ chip • The Rochester cube • Near and long ‐ term research problems • Conclusions 4
Break Through the Interconnect Wall 5 Presentation Outline • Three ‐ dimensional (3 ‐ D) integration – Opportunities for 3 ‐ D ICs – Forms of 3 ‐ D integration – Challenges for 3 ‐ D ICs • MIT Lincoln Laboratories 3 ‐ D Technology • Physical design issues in 3 ‐ D integration • 3 ‐ D networks ‐ on ‐ chip • The Rochester cube • Near and long ‐ term research problems • Conclusions 6
3 ‐ D Integration Maximum wirelength reduction 2 planes ~30% 4 planes ~50% L L L 2 L L 2 L 2 2 • Area = L 2 • Corner to corner distance = 2L • Area = L 2 • Area = L 2 L • Corner to corner distance ≈ L • Corner to corner distance ≈ 2 7 Advantages of 3 ‐ D Integration • Integration of disparate technologies – No yield compromise – Greater functionality • Number and length of global interconnects are reduced – Reduction in interconnect power • Dedicated NoC plane for IP block level communication M. Koyanagi, et al. , “Future System ‐ on ‐ Silicon LSI Chips,” IEEE Micro , Vol. 18, No. 4, pp. 17 ‐ 22, July/August1998.
Presentation Outline • Three ‐ dimensional (3 ‐ D) integration – Opportunities for 3 ‐ D ICs – Forms of 3 ‐ D integration – Challenges for 3 ‐ D ICs • MIT Lincoln Laboratories 3 ‐ D Technology • Physical design issues in 3 ‐ D integration • 3 ‐ D networks ‐ on ‐ chip • The Rochester cube • Near and long ‐ term research problems • Conclusions 9 Forms of 3 ‐ D Integration • Contactless 3 ‐ D circuits • Wire bonded die Transmitter Receiver • Stacked 3 ‐ D circuits • 3 ‐ D ICs – Fine grain interconnects Si 3 N 4 V DD V OUT Al V ss n + p PSG n + n + n + SiO 2 p + p + Bulk CMOS Si n 10
Cross ‐ Section of a 3 ‐ D Integrated Circuit •Different plane bonding styles •Bonding process involves – Wafer thinning •Bonding materials Through silicon vias (TSV) Substrate Intraplane 3rd plane Interconnects Adhesive polymer Substrate Intraplane 2nd plane Interconnects Adhesive polymer 1st plane Devices Bulk CMOS *R. J. Gutmann et al ., “Three ‐ Dimensional (3D) ICs: A Technology Platform for Integrated Systems and Opportunities for New Polymeric Adhesives,” Proceedings of the Conference on Polymers and Adhesives in Microelectronics and 11 Photonics , pp. 173 ‐ 180, October 2001 Presentation Outline • Three ‐ dimensional (3 ‐ D) integration – Opportunities for 3 ‐ D ICs – Forms of 3 ‐ D integration – Challenges for 3 ‐ D ICs • MIT Lincoln Laboratories 3 ‐ D Technology • Physical design issues in 3 ‐ D integration • 3 ‐ D networks ‐ on ‐ chip • The Rochester cube • Near and long ‐ term research problems • Conclusions 12
Spectrum of Challenges in 3 ‐ D ICs 13 Presentation Outline • Three ‐ dimensional (3 ‐ D) integration • MIT Lincoln Laboratories 3 ‐ D Technology • Physical design issues in 3 ‐ D integration • 3 ‐ D networks ‐ on ‐ chip • The Rochester cube • Near and long ‐ term research problems • Conclusions 14
3D Integration for Integrated Circuits and Advanced Focal Planes Craig Keast, Brian Aull, Jim Burns, Nisha Checka, Chang-Lee Chen, Chenson Chen, Jeff Knecht, Brian Tyrrell, Keith Warner, Bruce Wheeler, Vyshi Suntharlingam, Donna Yost keast@LL.mit.edu MIT Lincoln Laboratory * This work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government . MIT Lincoln Laboratory Motivation for 3-D Circuit Technology Reduced Interconnect Delay High Bandwidth Exploiting Different -Processors Process Technologies Advanced Mixed Material Focal Planes System Integration MIT Lincoln Laboratory
Pad-Level “3D Integration” Die Stacking Stacked-Die Wire Bonding Stacked Chip-Scale Packages 1 mm ChipPAC, Inc. Tessera, Inc. MIT Lincoln Laboratory In Production! Approaches to High-Density 3D Integration (Photos Shown to Scale) Tier-1 3D-Vias Tier-3 3D-Vias Tier-2 10 m Tier-1 Tier-2 10 m 10 m Photo Courtesy of RTI Bump Bond used to Two-layer stack with Three-layer circuit using flip-chip interconnect insulated vias through MIT-LL’s SOI-based vias two circuit layers thinned bulk Si MIT Lincoln Laboratory
Advantages of Silicon-on-Insulator (SOI) for 3-D Circuit Integration SOI Cross-Section • The electrically active portion Bonding Layer of an integrated circuit wafer is < 1% of the total wafer Buried Oxide thickness Handle Silicon Oxide ~6 m • Buried oxide layer in SOI provides ideal etch stop for ~675 m wafer thinning operation prior to 3D integration • Full oxide isolation between transistors allows direct 3D via formation without the added complexity of a via isolation layer • SOI’s enhanced low-power operation (compared to bulk CMOS) reduces circuit stack heat load MIT Lincoln Laboratory 3-D Circuit Integration Flow-1 • Fabricate circuits on SOI wafers – SOI wafers greatly simplify 3D integration • 3-D circuits of two or more active silicon layers can be assembled Buried Oxide Wafer-1 can be either Bulk or SOI Wafer-1 Handle Silicon Buried Oxide Wafer-2 Handle Silicon Buried Oxide Wafer-3 Handle Silicon MIT Lincoln Laboratory
3-D Circuit Integration Flow-2 • Invert, align, and bond Wafer-2 to Wafer-1 Wafer-2 Handle Silicon Buried Oxide Wafer bond Wafer-1 • Remove handle silicon from Wafer-2, etch 3D vias, deposit and CMP damascene tungsten interconnect metal “Back Metal(s)” IC2 Tier-2 Concentric 3D Via Tier-1 Wafer-1 Handle Silicon MIT Lincoln Laboratory 3-D Circuit Integration Flow-3 • Invert, align, and bond Wafer-3 to Wafer-2/1-assembly, remove Wafer-3 handle wafer, form 3D vias IC3 Tier-3 IC2 Tier-2 Tier-1 Wafer-1 Handle Silicon • Etch Bond Pads Tier-3 IC3 Tier-2 IC2 Tier-1 Wafer-1 Handle Silicon MIT Lincoln Laboratory IEEE Trans. on Electron Devices, Vol. 53, No. 10, October 2006
3D-Specific Enabling Technologies T( o C) 500450 400 350 450 400 350 300 300 250 250 200 150 150 10000 Surface Energy (mJ/m 2 ) 1000 1 hr. 1 hr. o C, 10 h o C, 10 hr 275 275 10 hr. 10 hr. E a =0.14eV E a =0.14eV 100 1.2 1.2 1.4 1.4 1.6 1.6 1.8 1.8 2.0 2.0 2.2 2.2 2.4 2.4 1000/T ( o K -1 ) Low temperature oxide-bond process Bond Interface Precision wafer-wafer alignment High-density 3D-Via MIT Lincoln Laboratory MIT-LL 3D Via History (Photos Shown with Same Scale and Drawn 3D Via Size) 3 m 2 m 1.75 m 1.0 m Oct 2000 Dec 2004 May 2005 Sept 2006 oxide bond epoxy bond 64 x 64, 50- m Scaled 3D via 10um pixel LADAR 3 1024×1024, 8- μ m pixel 64 x 64, 12- μ m visible image sensor 2 active-pixel sensor 1 [1] J. Burns, et al., “Three-dimensional integrated circuits for low-power high-bandwidth systems on a chip,” in Proc. Papers IEEE Int. Solid- State Circuits Conf. Tech. Dig. , 2001, pp. 268-269. [2] V. Suntharalingam, et al., “Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology,” in Proc. Papers IEEE Int. Solid-State Circuits Conf. Tech. Dig. , 2005, pp. 356-357. [3] B. Aull, et al., “Laser radar imager based on three-dimensional integration of Geiger-mode avalanche photodiodes with two SOI timing- circuit layers,” in Proc. Papers IEEE Int. Solid-State Circuits Conf. Tech. Dig. , 2006, pp. 304-305. MIT Lincoln Laboratory
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