CSCI341 Lecture 36, Pipelining & Hazards RECALL... RECALL... - PowerPoint PPT Presentation

CSCI341 Lecture 36, Pipelining & Hazards

RECALL...

RECALL... HAZARDS • Data Hazards • Control Hazards Dukes of Hazzard

DATA HAZARD Hardware solution: Include forwarding paths in the machine’s datapath. Even though results have not yet reached the writeback stage, the needed information is forwarded from a pipeline register to the input of the ALU (for example).

HAZARD “DETECTION” • Control logic inspects instruction registers used by neighboring stages. • eg, “If EX/MEM’s Rd = ID/EX’s Rs and EX/MEM’s Rd = ID/ EX’s Rt”

HAZARD

FORWARDING

“FORWARDING UNIT”

DATA HAZARD Can’t always solve this w/ hardware. For example: lw followed by add

DATA HAZARD

DATA HAZARD One solution: Rearrange the assembly instructions so the instruction following a load is not one that uses the value fetched from memory. (Pipelined loads are often called “delayed loads.”)

DATA HAZARD What if the instructions can’t be rearranged? Then we insert a nop instruction. (“No Operation”)

NOP 0000 0000 0000 0000 0000 0000 0000 0000 ( sll $0, $0, 0 )

STALLING

HAZARD DETECTION

CONTROL HAZARDS Associated with every branch/jump instruction.

ONE SOLUTION Assume the branch is not taken. (If it is, then we must flush the instructions that have already begun flowing through the pipeline.)

AN IMPROVED SOLUTION Determine the branch condition earlier (using additional logic circuitry.) The goal is to slightly reduce the number of “wasted” instructions (and cycles) that have entered the pipeline.

DELAY SLOT At the assembly level, organize the instructions such that the instruction immediately following a branch instruction is a useful one. Loop: Loop: add $t0, $t0, $v0 addi $v0, $v0, -1 addi $v0, $v0, -1 bnez $v0, Loop bnez $v0, Loop add $t0, $t0, $v0 li $v0, 4 li $v0, 4 ... ...

DYNAMIC BRANCH PREDICTION In a nutshell: Keeping track of branch instruction histories, and consulting previous branch decisions to best predict the current one.

EXCEPTIONS aka “Interrupts” I/O device request Invoke the OS Overflow HW Malfunction Important when considering pipelined architectures!

WHAT HAPPENS? Save the address of the exceptional instruction (in the EPC, exception program counter). Transfer control to the OS at some specified address. OS can terminate the program or continue.

OS EXCEPTION HANDLING • What was the reason? (MIPS uses a “cause register”) • Which instruction was the culprit? (EPC)

EXCEPTIONS & PIPELINING In essence, an exception is treated like a control hazard.

NEXT.... Parallelism

HOMEWORK • Reading 30 • Project 8: “Flip Ya!” Flip it good!