CS152: Discussion Section 1 Introduction / Microprogramming / Lab 1 - PowerPoint PPT Presentation

Welcome Arch vs µ arch Microcode Lab 1 Overview CS152: Discussion Section 1 Introduction / Microprogramming / Lab 1 Overview Albert Ou, Yue Dai Department of Electrical Engineering and Computer Sciences University of California, Berkeley January 31, 2020 CS152 Section 1 2020-01-31 1 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Welcome CS152 Section 1 2020-01-31 2 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Meet your GSIs Albert Ou • Email: aou@eecs.berkeley.edu • Office Hours: Monday 3pm-4pm, 326 Soda Hall • PhD student (advised by Krste Asanovi´ c) • Research focus: Vector architectures, data-parallel accelerators • CS152 survivor from long ago (2012) CS152 Section 1 2020-01-31 3 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Meet your GSIs Yue Dai • Email: yuedai96@berkeley.edu • Office Hours: Tuesday 4:30pm-5:30pm, 347 Soda Hall • PhD student (advised by Borivoje Nikoli´ c) • Research focus: Massive MIMO transceiver baseband system (6 + G) CS152 Section 1 2020-01-31 4 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Agenda 1 Architecture vs microarchitecture 2 Microcoding review 3 Lab 1 overview CS152 Section 1 2020-01-31 5 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Administrivia • Problem Set 1 due at 10:30am Mon, Feb 10 • Lab 1 due at 10:30am Wed, Feb 19 • Submit assignments through Gradescope • https://www.gradescope.com/courses/84575 • Join with code 9VZ526 • Check course webpage for schedule • http://www-inst.eecs.berkeley.edu/~cs152/sp20/ • Sign up for Piazza • http://piazza.com/berkeley/spring2020/cs152 CS152 Section 1 2020-01-31 6 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Arch vs µ arch CS152 Section 1 2020-01-31 7 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview What is an ISA? “The term architecture is used here to describe the attributes of a system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flow and control, the logic design, and the physical implementation.” G. M. Amdahl, G. A. Blaauw, and F. P. Brooks, “Architecture of the IBM system/360,” IBM Journal of Research and Development , vol. 8, no. 2, pp. 87–101, Apr. 1964 CS152 Section 1 2020-01-31 8 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Architecture vs Microarchitecture Architecture : the instruction set Q: What are some examples of ISAs? (What might you find in a server? In a mobile device?) Microarchitecture : the implementation (organization) of an architecture Q: Is it necessarily hardware? Q: What might be the fastest RISC-V implementation publically available? CS152 Section 1 2020-01-31 9 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview What does it mean to be architecturally visible ? Instructions perform operations on architecturally visible state to do useful work. Q: Is the following exposed by the architecture (true/false)? 1 Register file entries in a classical RISC 5 NOPs pipeline 6 Pipeline bubbles 2 The stack in a stack architecture 7 Condition code/flags 3 Pipeline registers 8 Memory address width 4 Branch-delay/load-delay slots 9 Instruction/data caches CS152 Section 1 2020-01-31 10 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Classifying ISAs based on addressing modes (Computer Architec- ture, A Quantitative Approach: Appendix A) CS152 Section 1 2020-01-31 11 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Power of Abstraction ISA – “most important interface in computer system” • Where hardware meets software • Simple does not necessarily mean less functional • Just 101 RISC-V instructions are sufficient to run a full OS (GNU/Linux) and applications! • User-level: RV64I (40+15) + M (8+5) + A (11+11) • Privileged: Sv39 (7+4) • Optional: F (26+4) + D (26+6) + C (45) CS152 Section 1 2020-01-31 12 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Power of Abstraction How to bootstrap a new ISA • How many lines of code (C, assembly) needed to port a kernel and toolchain? Linux : 113 files changed, 10307 insertions(+), 1 deletion(-) gcc : 67 files changed, 10295 insertions(+), 11 deletions(-) binutils : 56 files changed, 9982 insertions(+), 20 deletions(-) glibc : 178 files changed, 15169 insertions(+), 5 deletions(-) • ∼ 90% of Debian packages built for RV64 (Q2 2019; “buster”) • Out of 25,283 source packages • Out of 1,018,427,218 source lines of code CS152 Section 1 2020-01-31 13 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview So easy a dozen grad students can do it! • EOS22 tape-out (2014) • IBM 45nm SOI process • 1.65 GHz core frequency • 1st or 2nd RISC-V chip to boot Linux • C. Sun, M. T. Wade, Y. Lee, et al. , “Single-chip microprocessor that communicates directly using light,” Nature , vol. 528, p. 534, Dec. 2015 CS152 Section 1 2020-01-31 14 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Microcode CS152 Section 1 2020-01-31 15 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Microprogramming • Separation of datapath (arithmetic, data movement) from control (sequencing of operations on datapath) • Microcode program is essentially a description of a finite state machine • Implements an “interpreter” for a software-visible ISA (e.g., RISC-V) • Each microinstruction corresponds to one “state” • Microinstruction specifies outputs for given state and the next state CS152 Section 1 2020-01-31 16 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Single-Bus Datapath busy? IntRq Opcode zero? 32(PC) ldIR ALUOp ldA ldB 1(RA) ldMA rd rs1 rs2 1 RegSel MA addr addr IR A B 32 GPRs + Memory ImmSel PC Immed RegWr MemWr Select ALU (32-bit enReg enMem registers) enImm enALU data data Bus CS152 Section 1 2020-01-31 17 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Microcoded vs Pipelined Q: How does a microcoded implementation differ from a classical RISC pipeline? Consider how the various instruction execution phases are implemented: • Instruction fetch • Instruction decode • Register read • ALU operations • Optional memory operations • Optional register writeback • Next instruction address (PC) calculation Q: Why does microcoding generally facilitate a simpler microarchitecture? CS152 Section 1 2020-01-31 18 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Historical Context Q: Why did microcoding make sense historically? • ROM was cheaper and faster than logic • Simplified control complexity (helps verification) • CISC yielded better code density (Do these still hold true today?) CS152 Section 1 2020-01-31 19 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Historical Context Recurring theme in architecture: • Design choices are influenced by the limitations of available circuit technology • Re-evaluation becomes necessary as technology changes Avoid repeating past mistakes. . . but also know when old lessons may not apply CS152 Section 1 2020-01-31 20 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Preemptive Clarification Note: MemEn and RegEn are treated differently in the lecture and handout Busy? 32 (PC) MALd Busy? rs1 rs1 rs2 MemW rd rs2 RegW rd MALd 32(PC) RegSel 1 (ra) Address MA RegSel Register RAM Mem. Address Registers Main PC Memory Register Main RegW MemW RAM Memory RegEn MemEn Data Out In RegEn MemEn Lecture Handout CS152 Section 1 2020-01-31 21 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Preemptive Clarification Write/Read ChipEnable MemEn and RegEn semantics Lecture : Enable for tri-state buffer only Handout : General “chip enable” (CE) addr we • Must also be asserted for writes, dout not only reads bus din • Nothing happens with memory RAM if de-asserted (logical 0) Array (internal details from handout ) CS152 Section 1 2020-01-31 22 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Preemptive Clarification Tri-state buffers versus multiplexors encoder Bus using N tri-state buffers Bus using N :1 mux tree • Microcoded implementation in Lab 1 (Sodor) uses a mux tree instead of tri-state buffers to drive the bus • Functionally equivalent; friendlier to logic synthesis • Easier mapping to ASIC standard cells and FPGA CLBs • Design simplicity is worth the marginal area overhead CS152 Section 1 2020-01-31 23 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Preemptive Clarification Takeaways • We will adhere to the lecture’s convention for convenience • Handout will be eventually updated to match • Will be clarified in exam questions • Many approaches are valid depending on implementation style • Be aware that old exam/quiz solutions may use differing conventions • When in doubt, state your assumptions clearly in answers CS152 Section 1 2020-01-31 24 / 32

Welcome Arch vs µ arch Microcode Lab 1 Overview Lab 1 Overview CS152 Section 1 2020-01-31 25 / 32