Course Summary for the Quiz ECE 65, Winter2013, F. Najmabadi - PowerPoint PPT Presentation

Course Summary for the Quiz ECE 65, Winter2013, F. Najmabadi

Devices

Diode iv characteristics equation ( ) = − / v D nV 1 i I e T D S I S : Reverse Saturation Current (10 -9 to 10 -18 A) V T : Volt-equivalent temperature (= 26 mV at room temperature) n : Emission coefficient (1 ≤ n ≤ 2 for Si ICs) ≥ For | | 3 v nV D T ≈ / v nV Forward bias : i I e D T D S ≈ − Reverse bias : i I D S Sensitive to temperature:  I S doubles for every 7 o C increase  V T = T (k) /11,600 For derivation of diode iv equation, see Sedra & Smith Sec. 3 F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (3/22)

Diode piecewise-linear model: Diode iv is approximated by two lines Constant Voltage Model Diode ON Diode OFF V D0 Circuit Models: = ≥ Diode ON : and 0 ON: v V i 0 D D D = < Diode OFF : 0 and i v V 0 D D D = − " cut - in" voltage, 0 . 6 0 . 7 V for Si V D 0 OFF: F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (4/22)

Zener Diode piecewise-linear model = ≥ Diode ON : and 0 v V i 0 D D D = − < < Diode OFF : 0 and i V v V 0 D Z D D = − ≤ Zener : and 0 v V i D Z D Diode ON Circuit Models: Diode OFF ON: V D0 OFF: Zener Zener: F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (5/22)

Recipe for solving diode circuits Recipe: 1. Draw a circuit for each state of diode(s). 2. Solve each circuit with its corresponding diode equation. 3. Use the inequality for that diode state (“range of validity”) to check o if the solution is valid if circuit parameters are all known. o to find the range of circuit “variable” which leads to that state. F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (6/22)

Accuracy of Constant-Voltage Model Constant Voltage Model Diode ON In forward bias, diode voltage changes slightly as current changes (discussed later in small signal model) Diode OFF V D0 Diode can be in forward bias with v D as In forward bias, “cut -in” voltage ( V D0 ) small as 0.4 V when i D is small (Lab 4) can vary between 0.6 & 0.8 V ( ± 0.1 V) F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (7/22)

BJT iv characteristics includes four parameters NPN transistor Cut-off : = = 0 , 0 i i B C BE is reverse biased i I = = / v V C S i e BE T Active: β β B BE is forward biased  +  v BC is reverse biased    Two transistor parameters can be = / v V CE 1 i I e   BE T C S   V written in terms of the other four: A = + KCL : i i i E C B I = − = / (Deep) Saturation: v V KVL : S v v v i e BE T β BC BE CE B BE is forward biased  BJT iv characteristics equations are: ≈ < β BC is foward biased , v V i i = CE sat C B ( ) i f v B BE = ( , ) i g i v C B CE F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (8/22)

Transistor operates like a “valve:” i C & v CE are controlled by i B Controlled part: i C & v CE are set by transistor state (& outside circuit) Controller part: Circuit connected to BE sets i B BJT Linear Model  Cut-off ( i B = 0, v BE < V D 0 ): Valve Closed i C = 0,  Active ( i B > 0, v BE = V D 0 ): Valve partially open i C = β i B, v CE > V D 0  Saturation ( i B > 0 , v BE = V D 0 ): Valve open i C < β i B, v CE = V sat  For PNP transistor, replace v BE with v EB and replace v CE with v EC in the above. = = For Si, 0 . 7 V , 0 . 2 V V V 0 D sat * BJT Linear model is based on a diode “constant-voltage” model for the BE junction and ignores Early effect. F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (9/22)

Recipe for solving BJT circuits (State of BJT is unknown before solving the circuit) 1. Write down BE-KVL and CE-KVL: 2. Assume BJT is OFF, Use BE-KVL to check: BJT OFF: Set i C = 0, use CE-KVL to find v CE (Done!) a. BJT ON: Compute i B b. Assume BJT in active. Set i C = β i B . Use CE-KVL to find v CE . 3. If v CE ≥ V D 0 , Assumption Correct, otherwise in saturation: BJT in Saturation. Set v CE = V sat . Use CE-KVL to find i C . 4. (Double-check i C < β i B ) NOTE: o For circuits with R E , both BE-KVL & CE-KVL have to be solved simultaneously. F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (10/22)

MOS i-v Characteristics Equations NMOS PMOS NMOS ( V OV = v GS – V tn ) ≤ = Cut - Off : 0 0 V i OV D [ ] W ≥ ≤ = µ − 2 Triode : 0 and 0 . 5 2 V v V i C V v v OV DS OV D n ox OV DS DS L [ ] W ≥ ≥ = µ + λ 2 Saturation : 0 and 0 . 5 1 V v V i C V v OV DS OV D n ox OV DS L o For PMOS set V OV = v SG – | V tp | & replace v DS with v SD in the above F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (11/22)

MOS operation is “Conceptually” similar to a BJT -- i D & v DS are controlled by v GS Controlled part: i D & v DS are set by transistor state (& outside circuit) Controller part: Circuit connected to GS sets v GS (or V OV )  A similar solution method to BJT: o Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve with the corresponding MOS equation and validate the assumption.  MOS circuits are simpler to solve because i G = 0 ! o However, we get a quadratic equation to solve if MOS in triode (check MOS in saturation first!) F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (12/22)

Functional Circuits

Rectifier & Clipper Circuits Half-wave rectifier ≥ = − For , (Diode ON) v V v v V 0 0 i D o i D < = For , 0 (Diode OFF) v V v 0 i D o Clipper ≥ = For , ( Diode ON) v V v V 0 0 i D o D < = For , ( Diode OFF) v V v v 0 i D o i F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (14/22)

“Clipping” voltage can be adjusted v o limited to ≤ V D0 + V DC v o limited to ≤ V D0 + V Z v o limited to ≥ − V D0 − V DC v o limited ≥ − V D0 − V Z F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (15/22)

Both top & bottom portions of the signal can be clipped simultaneously v o limited to ≤ V D0 + V DC1 and ≥ − V D0 − V DC2 v o limited to ≤ V D0 + V Z1 and ≥ − V D0 − V Z2 F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (16/22)

Peak Detector & Clamp Circuits Peak Detector Circuit  “ideal” peak detector: τ /T → ∞  “Good” peak detector: τ /T >> 1 Clamp Circuit v o is equal to v i but shifted “downward” by − ( V + − V D0 ) F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (17/22)

Voltage shift in a clamp circuit can be adjusted! v o shifted “downward” + + = − − − = − − − ( ) ( ) v v V V V v v V V V o i DC D 0 o i Z D 0 v o shifted “upward” − − = + − − = + − − ( ) ( ) v v V V V v v V V V o i DC D 0 o i Z D 0 F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (18/22)

BJT as a switch Load is placed in collector circuit  Use: Logic gate can turn loads ON (BJT in saturation) or OFF (BJT in cut-off)  i c is uniquely set by CE circuit (as v ce = V sat )  R B is chosen such that BJT is in deep saturation with a wide margin (e.g., i B = 0.2 i c / β ) *Lab 4 circuit Solved in Lecture notes (problems 12 & 13) F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (19/22)

BJT as a Digital Gate Resistor-Transistor logic (RTL) RTL NOT gate ( V L = V sat , V H = V CC ) RTL NOR gate* RTL NAND gate*  Other variants: Diode-transistor logic (DTL) and transistor-transistor logic (TTL)  BJT logic gates are not used anymore except for high-speed emitter-coupled logic circuits because of o Low speed (switching to saturation is quite slow). o Large space and power requirements on ICs *Solved in Lecture notes (problems 14 & 15) F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (20/22)

NMOS Functional circuits  Similar to a BJTs in the active mode, NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)  Transition from cut-off to triode can be used to build NMOS switch circuits. o Voltage at point C (see graph) depends on NMOS parameters and the circuit (in BJT v o = V sat )!  We can also built NMOS logic gate similar to a RTL. But there is are much better gates based on CMOS technology! F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (21/22)

Complementary MOS (CMOS) is based on NMOS/PMOS pairs  Maximum signal swing: Low State: 0, High State: V DD o Independent of MOS device parameters!  Zero “static” power dissipation ( i D = 0 in each state). o It uses the fact that if a MOS is ON and i D = 0 only if MOS is in triode and v DS = 0 CMOS NAND Gate CMOS Inverter F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (22/22)