Compositional correctness of IP-based system design: Translating - PowerPoint PPT Presentation

Compositional correctness of IP-based system design: Translating C/C++ Models into SIGNAL Processes Rennes, November 04, 2005 Hamoudi Kalla and Jean-Pierre Talpin Espresso Team

Outline � Introduction � Preliminaries � Translating C/C++ Models into SIGNAL Processes � Principles � Example � Implementation � Conclusion and Future works 2

Introduction C/C++ System Design Validation � Simulators and test tools � They may not cover all design errors � We need formal verification to ensure the quality of system designs � we need formal models 3

System Design Validation Using Formal Models Our Methodology C/C++ Models C/C++ Models automatic translation Formal Models : Formal Models : SIGNAL processes SIGNAL processes 4

Preliminaries � Control Data-Flow Graph (CDFG) � Single Statement Assignment (SSA) 5

Preliminaries Control Data Flow Graph � Represents a procedure or a program as a directed graph G=(V, E), where the set V represents control flow nodes and E represents jumps in the control flow � Control Flow nodes are Basic blocks, Test blocks, and Join Blocks 6

Preliminaries Control Data Flow Graph: Nodes int example(int a, int b, int c) { int x, y, z, result; y = a * b; z = a * c; if (y>z) x = y – z; else x = z – y; result = x * a; return result; } C/C++ program CDFG 7

Preliminaries Control Data Flow Graph: Nodes � Basic Blocks (BB) are instructions without any jumps. � Test blocks (T) describe conditional branching expressions. � Join blocks (J) represent the end of conditional branches. CDFG 8

Preliminaries Single Statement Assignment (SSA) Form � SSA is a form of Control Data Flow Graph that allows optimizations to be done efficiently and easily � In SSA, every variable receives exactly one assignment during its lifetime … … x = a * b; SSA x1 = a * b; x = a * c; x2 = a * c; … … 9

Preliminaries Single Statement Assignment (SSA) Form New function its associated Static Single Control Data Flow Graph Assignment form 10

Translating C/C++ Models into SIGNAL Processes C/C++ Models C/C++ Models SSA Form GCC ? SIGNAL processes SIGNAL processes 11

Translating C/C++ Models into SIGNAL Processes C/C++ Models C/C++ Models functions f 1 , …, f n f 1 � SSA 1 GCC … ? f n � SSA n … SSA 1 � process 1 … SSA n � process n SIGNAL processes SIGNAL processes 12

Translating C/C++ Models into SIGNAL Processes Principle Encode nodes, edges, assignment statement, conditional branching, and Ф function Function f Process f (SSA) (SIGNAL) 13

Translating C/C++ Models into SIGNAL Processes Encoding SSA Nodes (blocks) Boolean BB1, T2, BB2, x BB3, J1, BB4; Instants t1 t2 t3 t4 t5 … t1 t2 t3 t4 t5 … BB1 true false false false false … BB1 true false false false false … T2 false true false false false … T2 false true false false false … BB2 false false true false false … BB2 false false true false false … blocks BB3 false false false true false … BB3 false false false true false … J1 false false false false true … J1 false false false false true … BB4 false false false false true … BB4 false false false false true … 14

Translating C/C++ Models into SIGNAL Processes Encoding SSA Edges : for Basic and Test blocks B1 | B2 : = true when pre_B1 default false B2 | pre_B1 : = B1$ init false t1 t2 t3 t4 t5 … t1 t2 t3 t4 t5 … B1 true false false false false … B1 true false false false false … pre_B1 false true false false false … pre_B1 false true false false false … B2 false true false false false … B2 false true false false false … 15

Translating C/C++ Models into SIGNAL Processes Encoding SSA Edges : for Join blocks B1 B2 | J1 : = true when pre_B1 default true when pre_B2 default J1 false t1 t2 t3 t4 t5 … t1 t2 t3 t4 t5 … pre_B2 false true false false false … pre_B2 false true false false false … pre_B1 false false false false false … pre_B1 false false false false false … J1 false false true false false … J1 false false true false false … 16

Translating C/C++ Models into SIGNAL Processes Encoding Assignment Statement B1 | x1 : = ( y1 + z1 ) when B1 default x1$ X1 = y1 + z1 X1 = y1 + z1 t1 t2 t3 t4 t5 … t1 t2 t3 t4 t5 … B1 false true false false false false … B1 false true false false false false … Pre_B1 false false true false false false … Pre_B1 false false true false false false … x1 0 5 5 5 5 5 … x1 0 5 5 5 5 5 … y1 2 2 2 2 2 2 … y1 2 2 2 2 2 2 … z1 3 3 3 3 3 3 … z1 3 3 3 3 3 3 … 17

Translating C/C++ Models into SIGNAL Processes Encoding Conditional Branching Statement T1 | test1 : = (x>y) when T1default false If (x>y) goto B1; If (x>y) goto B1; | pre_test1 : = test1$ init false else goto B2; else goto B2; | B1 : = true when pre_test1 B1 B2 when pre_T1 default false | B2 : = true when not pre_test1 when pre_T1 default false t1 t2 t3 t4 t5 … t1 t2 t3 t4 t5 … T1 false true false false false … T1 false true false false false … pre_T1 false false true false false … pre_T1 false false true false false … Test1 false true false false false … Test1 false true false false false … pre_test1 false false true false false … pre_test1 false false true false false … B1 false false true false false … B1 false false true false false … B2 false false false false false … B2 false false false false false … 18

Translating C/C++ Models into SIGNAL Processes Encoding Ф Function B1 B2 X1 = … X2 = … X1 = … X2 = … J1 | x3 : = x1 when pre_B1 default x2 X3 = Ф (x1,x2) X3 = Ф (x1,x2) B3 Y = x3 + … Y = x3 + … 19

Translating C/C++ Models into SIGNAL Processes Encoding Loop Statement : Blocks B0 … … | test1 : = (x>y) when T1default false J1 | pre_test1 : = test1$ init false … … T1 | T1 : = true when pre_B0 default If (x>y) goto B1; If (x>y) goto B1; true when pre_B1 default false else goto B2; else goto B2; | B1 : = true when pre_test1 B1 when pre_T1 default false … … B2 | B2 : = true when not pre_test1 … … when pre_T1 default false 20

Translating C/C++ Models into SIGNAL Processes Encoding Loop Statement : statements B0 | i1 : = 1 when B0 default i1$ i1 := 1 i1 := 1 J1 | i2 : = i1 when pre_B0 default i3 i2 := Ф (i1,i3) i2 := Ф (i1,i3) T1 If (i2<10) goto B1; If (i2<10) goto B1; else goto B2; else goto B2; B1 | i3 : = i2$ +1 when pre_B1 default i3$ i3 := i2 + 1 i3 := i2 + 1 B2 … … 21

Translating C/C++ Models into SIGNAL Processes Encoding pointers (1) B0 X = 10 X = 10 x = 10; T1 SSA if (T) p = &x ; If (T) goto B1; If (T) goto B1; else goto B2; else p = &y ; else goto B2; z = *p; B1 B2 p1 = &x p2 = &y p1 = &x p2 = &y Signal J1 p3 = Ф (p1,p2) p3 = Ф (p1,p2) p = (p_tag,p_star) p_tag = 0 � p = &x B3 p_start = x z = *p3 z = *p3 p_tag = 1 � p = &y p_start = y 22