CISC Design Hardware Flowchart Virendra Singh Associate Professor - PowerPoint PPT Presentation

CISC Design Hardware Flowchart Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in EE-739: Processor Design Lecture 5 CADSL

Micro-coded Implementation Bus Controller Clock-Phase Generator Instruction Instruction Control Sequencer Decoder Store Encoded Control Word Fields Instruction Prefetch Control Word Decoder Register Decoded Datapath Control Internal A Bus Address Data PC R0 R1 Rn Shifter ALU Out Reg. Reg. Internal B Bus Datapath CADSL 22 Jan 2013 EE-739@IITB 2

Instruction Execution ADD R1, D2(B2) ‘5A’ R1 B2 D2 0 8 12 16 31  The second operand is added in the first  The sum is placed in the first operand location  The operand and the sum are treated as 16-bit signed binary integers  The first operand is in the register specified by the R1 field  The second operand is in the memory – address is calculated by adding the displacement specified by the D2 field to the content of the base register specified by the B2 field CADSL 22 Jan 2013 EE-739@IITB 3

Execution Steps Steps for ADD instruction Execution 1. Fetch the first half word 2. Find ADD control word sequence 3. Fetch the remaining instruction word 4. Calculate the operand address 5. Fetch the operand 6. Add 7. Store the result CADSL 22 Jan 2013 EE-739@IITB 4

Execution Steps 1. Fetch the remaining instruction word 2. Calculate the operand address 3. Fetch the operand 4. Add 5. Store the result 6. Update the program counter 7. Fetch the first half word for the next instruction 8. Find the address of the next instructions control word sequence 9. Branch to the next instruction’s control word CADSL 22 Jan 2013 EE-739@IITB 5

Execution Steps 1. Fetch the remaining instruction word  One state to second half of the ADD instruction 2. Calculate the operand address  One state to add D2 displacement and the content of the B2 register 3. Fetch the operand  One state to fetch the data half word (put the address on the pads and wait for the operand half-word) 4. Add  One state to add the operands 5. Store the result  One state to store the result in Register R1 CADSL 22 Jan 2013 EE-739@IITB 6

Execution Steps 6. Update the program counter  One state to increament PC  One state to save the incremented value 6. Fetch the first half word for the next instruction  One state to put the PC value on the pads and wait for the first half of the next instruction 6. Find the address of the next instructions control word sequence  One state to put the next instruction into the instruction decoder 6. Branch to the next instruction’s control word  Zero state – this step is accomplished as a part of the previous step CADSL 22 Jan 2013 EE-739@IITB 7

Processor - Block Diagram Clock-Phase Reset & Power-On Logic Interrupt Logic Bus Controller Generator Next State Control IR Control Store Decoder Branch Control unit Encoded Control Word Fields Instruction Prefetch Control Word Decoder Register Decoded Datapath Control Internal A Bus Address Data PC R0 R1 Rn Shifter ALU Out Reg. Reg. Internal B Bus Datapath CADSL 22 Jan 2013 EE-739@IITB 8

Hardware Flowchart CADSL 22 Jan 2013 EE-739@IITB 9

Hardware Flowchart Pre-requisites:  Datapath  Instruction set  Programmer’s summary register set  Instruction Format  Additional  Operations registers  Addressing modes  ALU and any special functional  Registers units • Datapath will evolve  Internal data paths CADSL 22 Jan 2013 EE-739@IITB 10

Development of Implementation  The architecture specification is the only input Clock Phase Generator  Begin with a guess of Datapath  Do flowchart for the instructions  This modifies and refines the Datapath and develops the control store and control strategy Datapath  The final Datapath is derived output CADSL 22 Jan 2013 EE-739@IITB 11

Development of Implementation  Once flowcharts Clock Phase are fairly Generator complete, derive the control word Control Word format using the Control flowchart states Store  When the flowcharts are complete, so is the Datapath  Control word Datapath format is derived output CADSL 22 Jan 2013 EE-739@IITB 12

Development of Implementation Clock Phase  After defining Generator control word format, you assign bit Control Store patterns to the control fields in a way that minimizes Control Word Decoder control word decoders Datapath between the control store and the Datapath CADSL 22 Jan 2013 EE-739@IITB 13

Development of Implementation Clock Phase  Instruction Generator decoders are defined the Control flowcharts and Store Instruction the architecture Decoder specification Control Word Decoder Datapath CADSL 22 Jan 2013 EE-739@IITB 14

Development of Implementation Clock Phase Bus Controller  Completed Generator flowchars, control word Control format, and the Store Instruction initial bus Decoder specification defines the bus Control Word Decoder controller Datapath CADSL 22 Jan 2013 EE-739@IITB 15

Development of Implementation  Last is the logic of Clock Phase Bus Controller the state Generator sequencer, the part of the chip that says what to do Control State next (where is the Store Sequencer Instruction next control word?) Decoder  Once every thing around it is Control Word Decoder defined, you build exactly what you Datapath need! (The state sequencer is derived output) CADSL 22 Jan 2013 EE-739@IITB 16

Flowchart Objective Flowchart Objective  Limit controller size to some fraction of chip area  Make CPU as fast as possible  Complete the project as early as possible  Make the flowcharts easy to translate into hardware CADSL 22 Jan 2013 EE-739@IITB 17

Example: MIN Instruction Set Instruction Format Programmer’s Register Set First Word R0 Op-code Rx Mode Ry R1 R2 Operation First Second First Operand Operand Operand . Code Register Address Register . Mode . Second Word Rn Displacement Optional, depending on second operand address mode CADSL 22 Jan 2013 EE-739@IITB 18

MIN Instruction Set  ADD  AND  BZ – Branch if zero bit is set. (Register Indirect only)  LOAD – Second operand is source and Rx is destination  POP – Postincrement with register indirect only  PUSH – Predecrement with register indirect only  STORE  SUB  TEST CADSL 22 Jan 2013 EE-739@IITB 19

MIN Instruction Set Second Operand Address Mode Ry Second Operand First Operand Address Mode Register Address Modes  AB - Base (Ry) plus displacement (second instruction word) is an operand address  AI – Register indirect. Ry holds an operand address  AR – Register direct: The result is stored in Ry. For two operand instructions, Ry also is an operand source CADSL 22 Jan 2013 EE-739@IITB 20

MIN Datapath IRE IRF Internal A Bus DO AO PC T2 R0 R1 Rn T1 ALU k DI Internal B Bus External Data External Address Bus (EDB) Bus (EAB) CADSL 22 Jan 2013 EE-739@IITB 21

MIN Datapath Rules of Operation 1. A transfer from source to bus to destination takes one state time 2. A source can drive up to three destination loads 3. Inputs to the ALU are from A (internal) bus and either k (values 0, +1, -1) or the B (internal) bus 4. When ALU is destination. T1 is automatically loaded from the ALU output 5. A transfer to AO activates the on-chip external bus controller. This bus controller postpones the next state until the external transfer is complete. CADSL 22 Jan 2013 EE-739@IITB 22

Flowcharts ADD RX AR RY ADD RX AI (RY) Register-to-Registe r Register-to-Memory R  R ADD R  M ADD Rx  a  alu Edb  di State Ry  b  alu Ry  b  ao Di  b  alu T1  b  ry Sequence Rx  a  alu Ry  b  ao IRE IRF T1  a  do DO Internal A Bus AO PC T2 R0 R1 Rn T1 ALU k DI Internal B Bus CADSL 22 Jan 2013 EE-739@IITB 23