Challenges in Open-source RISC-V Implementations Differentiation & Customization
Open Source Hardware – Promises and Hopes • Great way to collaborate • Faster development thanks to readily available IP (e.g. peripherals, …) • Very good for academia • But not so much for the industry … Codasip GmbH 2
Open Source Hardware - Challenges … because there are still big challenges: o Is everything in place? o Who do I call for help? o What about physical design issues? Closing timing, etc. o Can it be customized without breaking it? o How can the modifications be verified? o How do I add new instruction support to the compiler? o … Codasip GmbH 3
Challenges – Possible Solutions • Do it yourself o Requires in-house expertise o Toolchain maintenance becomes burdensome and expensive • License off-the-shelf RISC-V processor o Most economical from overall cost-of-ownership • New organizations that will try to target some of the challenges Chip Alliance OpenHW lowRISC o But.... Customization can still be challenging or problematic • Use professional tools to make it easier o Still lower cost than DIY o Allows your team to focus on other critical areas of chip design Codasip GmbH 4
Open source costs • Creating a production worthy processor is a huge task o Whether it is from university, govt research, or commercial IP provider • Supporters of open cores have to extend the deliveries to add missing pieces to put the processor into silicon o Users need documentation, support, verification reports, synthesis scripts, simulation models, integration for virtual prototyping etc. Codasip GmbH 5
Example: Automotive and Open Source HW • ISO 26262 requires an enormous capital investment o Certification of design practices: ISO 9001 o Independent certification of processor design • Safety design requirements such as MPU, ECC on memories, watchdog timers, synch interface for lockstep. o Safety certification of C compiler • Which version? Change management? o Very long (>10 year) support and maintenance obligations • How can this be managed by the “community”? Codasip GmbH 6
Who is Codasip ? • The leading provider of RISC-V processor IP • Founded in 2014 in the Czech Republic Based on 10 years of university research on processor design automation o Founding member of the RISC-V Foundation, www.riscv.org o Now Codasip GmbH, with offices in Silicon Valley and Czech Republic o Codasip introduced its first RISC-V • Provides unique design automation tools for easy processor processor in November 2015 modification Delivers performance/power efficiency and low-cost o Algorithm accelerators (DSP , security, audio, video, etc.) o Profiling of embedded SW for tailoring processor IP o • Codasip Bk = portfolio of RISC-V processors Codasip GmbH 7
Bk: Customizable RISC-V Cores Bk = the Berkelium series, Codasip’s RISC -V processors. Multiple Options ✓ Available immediately ✓ Fully customizable ✓ Pre-verified, tape-out quality IP o Support for all RISC-V ISA standard extensions o Enable easy creation of performance-enhancing o Users do not need to verify IP resources, such as: ✓ Industry-standard interfaces Custom registers for computations • o AMBA for instruction and data bus Custom control-status registers • o JTAG (4pin/2pin) for debugging Novel interfaces such as GPIO, FIFO, scratch-pad • memory o Even pipeline modifications are possible Bk core CodAL source as the starting point for your own • RISC-V core Codasip GmbH 8
Codasip RISC-V IP Deliverables Hardware Development Kit (HDK) Software Development Kit (SDK) • Verilog RTL • Eclipse IDE • SystemVerilog UVM test environment • C/C++ LLVM Compiler (including SystemC co-simulation) • C/C++ Libraries (Newlib) • Automated test suite • Assembler, linker, disassembler (GNU based) • Sample EDA scripts • High performance instruction set and cycle accurate simulators • Debugger (enhanced GDB interface) Codasip GmbH 9
Toolchain • CodeSpace o Eclipse-based cockpit for software development • Tools o LLVM-based C Compiler (7.0.1) Codasip optimization improves passes that are already there, • or adds its own that improve code density or performance. • o Assembler is Codasip’s proprietary tool More powerful than LLVM-as • o Linker is based on GNU ld More powerful than LLVM LLD • The tools are generated by Studio, so when Studio contains a new version of LLVM or other tools, the toolchain is updated automatically. Codasip GmbH 10
Profiler • Part of SDKs • Profiling = dynamic form of analysis o Identifies places in source code that should be optimized. Applicable to: Applications running on an processor • The processor itself • • Two main modes: o Tracking/watching o Instrumentation/annotations • Codasip IP packages support both modes • Useful for instruction set extensions Codasip GmbH 11
Debugger • Part of SDKs • Works with both ISS and on-chip debugger • Aware of custom instructions o Disassembly view and instruction stepping • LLDB = open-source debugger built on libraries provided by LLVM and Clang o Clean architecture with easy-to-extend plugin system o Its own commands – mapping to gdb commands exists • Codasip integrates LLVM 7.0.1 in its Studio Codasip GmbH 12
CodeSpace: Eclipse-based IDE • SDK management You can change the SDK for a software project • with a few clicks • Profiler perspective Integration with profiler tools directly with editors • • Enhanced debugging perspective You can view ports, signals or pipeline • • On-chip debugging You can move from ISS to on-chip debugging • within the same environment with the same software project Codasip GmbH 13
Configuration and Custom Extensions RISC-V offers a wide range of ISA modules: However, it may not be enough for your application domain or if you are • I / E for integer instructions • M for multiplication and division looking for a key differentiator… • C for compact instruction • F / D for floating point operations • WIP: B , P , V , … RISC-V allows SDK must be aware High level Codasip has tools for this task: custom of the custom of automation Codasip Studio extensions extensions needed Codasip GmbH 14
What is Codasip Studio? A unique collection of tools for fast & easy modification of RISC-V processors. All-in-one , highly automated. Introduced in 2014, silicon-proven by major vendors. Customization of base instruction set: Codasip Studio CodAL – processor description language Single-cycle MAC • element i_mac { Custom crypto functions use reg as dst, src1, src2; RTL Automation • assembly { “mac” dst “,” src1 “,” src2 }; And many more… binary { OP_MAC dst src1 src2 0:bit[9] }; • semantics { rf[dst] += rf[src1] * rf[src2]; Complete IP package on output: }; }; C/C++ LLVM-based compiler SDK automation • C/C++ Libraries • Integrated processor development environment Assembler, disassembler, linker • ISS (incl. cycle accurate), debugger, profiler • UVM SystemVerilog testbench Verification Automation • Codasip GmbH 15
Bk Core Customization with Codasip Studio Start from Bk3/5/7 cores 1. Add instructions Your RISC-V CodAL 2. Add resources Profiling of embedded application SW Models 3. Modify pipeline enables processor optimizations 4. … Codasip Studio Toolset Your RISC-V Your RISC-V HDK SDK Hardware Design Kit Software Design Kit ISA extensions are quickly RTL models Compiler • • implemented and analyzed during Synthesis scripts Assembler • • design space exploration Verification models Linker • • and simulators Debugger • Virtual prototypes IDE etc • • Codasip Studio automatically generates all processor IP design kits and verifies for RISC-V compliance (you still need to verify your own resources and instructions). Codasip GmbH 16
Conclusion • Open Source Hardware • Codasip RISC-V Solutions o In the early stage o Reduce the cost of custom processor development o Great opportunity and it opens many doors Automation and usage of standards enable • custom processors to easily integrate into any o Still a lot of work in front of design environment us o Simplify custom processor o Won’t be used by programming everybody Generate open-source tools for any processor • type to deliver powerful technology that is easy to integrate o Enable extensible and fully custom processor methodologies Make small optimizations to proven processor IP , • or implement a completely unique processor solution Codasip GmbH 17
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