IWKS 3300: NAND to Tetris Spring 2019 John K. Bennett Boolean Logic Foundations of Global Networked Computing: Building a Modern Computer From First Principles This course is based upon the work of Noam Nisan and Shimon Schocken. More information can be found at (www.nand2tetris.org).
Boolean Algebra Some elementary Boolean functions: x Not(x) x y And(x,y) 0 1 0 0 0 Not(x) 1 0 0 1 0 1 0 0 And(x,y) 1 1 1 Or(x,y) x y Or(x,y) x y Nand(x,y) Nand(x,y) (functionally complete!) 0 0 0 0 0 1 0 1 1 0 1 1 Boolean functions: 1 0 1 1 0 1 1 1 1 1 1 0 f ( x , y , z ) ( x y ) z x y z 0 0 0 0 0 0 1 0 A Boolean function can be expressed using a logic 0 1 0 1 expression, a truth table or a schematic. 0 1 1 0 Important observation: 1 0 0 1 1 0 1 0 Every Boolean function can be expressed using 1 1 0 1 And, Or & Not, so, if your function can implement these 3, it is “functionally complete.” 1 1 1 0
All Boolean Functions of Two Variables How many for n variables?
Boolean Algebra Given: Nand(a,b), false We can build: Not(a) = Nand(a,a) true = Not(false) George Boole, 1815-1864 (“ A Calculus of Logic ”) And(a,b) = Not(Nand(a,b)) Or(a,b) = Not(And(Not(a),Not(b))) Xor(a,b) = Or(And(a,Not(b)),And(Not(a),b))) Etc. (i.e., any Boolean function) We can prove this!
Gate Logic Gate logic – a gate architecture designed to implement a Boolean function Elementary gates: Composite gates: Important distinction: Interface ( what ) VS implementation ( how ).
Gate Logic Interface a Xor out b Claude Shannon, 1916-2001 (“Symbolic Analysis of Relay and a b out Switching Circuits” ) 0 0 0 0 1 1 1 0 1 An (Inefficient) Implementation 1 1 0 a And Not out Or Not And b Xor(a,b) = Or(And(a,Not(b)),And(Not(a),b)))
Circuit Implementations a a b a b out a b out b 0 0 0 0 0 0 0 1 0 AND gate 0 1 1 1 0 0 OR gate 1 0 1 1 1 1 1 1 1 power supply power supply out out Diode Transistor Implementation of NAND From a theoretical perspective, physical realizations of logic gates are irrelevant. From an engineering perspective, physical realizations of logic gates are essential to performance.
Project 1: Elementary Logic Gates a b Nand(a,b) Given: Nand(a,b), false 0 0 1 0 1 1 1 0 1 Build: 1 1 0 Not(a) = ... true = ... Q: Why these particular 12 gates? And(a,b) = ... A: Since … Or(a,b) = ... They are commonly used gates They provide all the basic building Mux(a,b,sel) = ... blocks needed to build our computer. Etc. - 12 gates altogether.
Multiplexor a b sel out sel out 0 0 0 0 0 a 0 0 1 0 a 1 b 0 1 0 0 out Mux 0 1 1 1 b 1 0 0 1 1 0 1 0 1 1 0 1 sel 1 1 1 1 Proposed Implementation: based on Not, And, Or gates (since we can build all of these from NAND. See Lab Notes: Multiplexors can be used a “function generators.” For example, how might a 4:1 mux be used to generate all possible combinations of two Boolean variables?
Example: Building an AND Gate Contract: And.cmp When running your a b out 0 0 0 a .hdl on our .tst , And 0 1 0 out your .out should be 1 0 0 b 1 1 1 the same as the book’s . cmp. And.hdl And.tst CHIP And load And.hdl, { IN a, b; output-file And.out, compare-to And.cmp, OUT ; output-list a b out; // implementation missing set a 0,set b 0,eval,output; } set a 0,set b 1,eval,output; set a 1,set b 0,eval,output; set a 1, set b 1, eval, output;
Building an AND Gate Interface: And(a,b) = 1 exactly when a=b=1 a And out b And.hdl CHIP And { IN a, b; OUT out; // implementation missing }
Building an AND Gate Implementation: And(a,b) = Not(Nand(a,b)) a out b And.hdl CHIP And { IN a, b; OUT out; // implementation missing }
Building an AND Gate Implementation: And(a,b) = Not(Nand(a,b)) a a out in out out Nand Not x b b And.hdl CHIP And { IN a, b; OUT out; // implementation missing }
Building an AND Gate Implementation: And(a,b) = Not(Nand(a,b)) a a out out in out NAND NOT x b b And.hdl CHIP And { IN a, b; OUT out; Nand(a = a, b = b, out = x); Not(in = x, out = out) }
Building an AND Gate with LogicCircuit Equation: And(a,b) = Not(Nand(a,b)) a a out out in out NAND NOT x b b
Building an AND Gate in LogicCircuit
Building an AND Gate in LogicCircuit – NAND Gate First
Building an AND Gate in LogicCircuit – NAND First
How Will We Create the HDL Files? CHIP Nand { IN a, b; OUT out; PARTS: Nand2 (x1 = a, x2 = b, q = out); }
Building the AND Gate // This file was generated from LogicCircuit CircuitProject: And // This is beta release code. Please report bugs to jkb@colorado.edu // 1/21/2019 10:21:11 AM /* #83,254,54,183,54,227,48,16,54,71,204,246,252,72,82, 22,179,128,38,52,84,200,39,21,37,135,202,244,64,254, 32,165,13,213,118,124,21,225,106,253,87,42,119,17,226, 38,105,68,136,111,81,74,166,33,253,142,240,176,187,82, 108,81,105,218,101,26,236,174,243,221,147,211,200,167,63, 198,155,149,254,56,20,232,82,22,127,34,80,188,43,207, 14,124,60,172,244,243,50,163,172,143,165,195,81,115,105, 192,89,182,64,75,149,42,189,241,84,52,127,100,119,70, 209,132,210,49,248,200,56,25# */ CHIP And { IN a, b; OUT out; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = U0out, b = U0out, out = out); }
Building the XOR Gate a And Not out Or Not And b CHIP Xor { IN a,b; OUT out; PARTS: Not(in=a,out=Nota); Not(in=b,out=Notb); And(a=a,b=Notb,out=w1); And(a=Nota,b=b,out=w2); Or(a=w1,b=w2,out=out); }
A Better XOR Implementation … using only NAND gates Why is this better?
Building an XOR Gate in LogicCircuit
Create the HDL File “SaveAsHDL” //Xor.hdl CHIP Xor { IN a, b; OUT; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = a, b = U0out, out = U1out); Nand (a = U0out, b = b, out = U2out); Nand (a = U1out, b = U2out, out = out); }
Hardware Simulator (Book)
Testing the Xor Gate HDL
How Will We Test These HDL Files? “Load Chip” //Xor.hdl CHIP Xor { IN a, b; OUT; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = a, b = U0out, out = U1out); Nand (a = U0out, b = b, out = U2out); Nand (a = U1out, b = U2out, out = out); }
How Will We Test These HDL Files? “Load Script” // Xor.tst load Xor.hdl, output-file Xor.out, compare-to Xor.cmp, output-list a%B3.1.3 b%B3.1.3 out%B3.1.3; set a 0, set b 0, eval, output; set a 0, set b 1, eval, output; set a 1, set b 0, eval, output;
Hardware Simulator (demonstrating XOR gate construction) test HDL script program
Hardware Simulator HDL program
Hardware Simulator HDL program output file
How Will We Test These HDL Files? | a | b | out | Xor.cmp | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 | If (Xor.out == Xor.cmp) Xor.out | a | b | out | | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Testing the Xor gate using the N2T Hardware Simulator
Testing Logic in LogicCircuit
Project Materials: www.nand2tetris.org Project 1 web site And.hdl , And.tst , And.cmp files
Project 1 Tips Read the Introduction + Chapter 1 (my version) of the book Download the book’s software suite (if using your own computer) Download LogicCircuit (my version) (if using your own computer) Go through the hardware simulator tutorial Do Project 0.5 Check out the HDL Survival Guide: http://nand2tetris.org/software/HDL%20Survival%20Guide.html
Perspective Each Boolean function has a canonical representation The canonical representation is expressed in terms of And, Not, Or And, Not, Or can be expressed in terms of NAND alone Thus, every Boolean function can be realized by a standard programmable logic device (PLD) using NAND gates only a Mass production and b c . Universal building blocks, f(a,b,c) . or . unique topology and Gates, neurons, atoms, …
End Notes: Programmable Logic Device for 3-way functions a legend: active fuse and b blown fuse c . f(a,b,c) 8 and terms . or connected to the . same 3 inputs single or term connected to the and outputs of 8 and terms _ _ _ PLD implementation of f(a,b,c)= a b c + a b c (the on/off states of the fuses determine which gates participate in the computation)
End Notes: Universal Building Blocks, Unique Topology a b and c . f(a,b,c) . or . and Artificial Neuron
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