Beginning of Presentation CDEEP Autumn 2009 CMOS VLSI Design Lab - PowerPoint PPT Presentation

IIT Bombay Beginning of Presentation CDEEP Autumn 2009 CMOS VLSI Design Lab Mentor - II Presented By- Rasmi Ranjan Sahoo (EE705 TA) EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Introduction The following tutorial will demonstrate a step by step method for schematic driven Layout in MentorG. Name of the tool for Schematic Driven Layout is ICSTATION . EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Including Rule Files •Make sure that the following rule files are included at the time of creating new project. Rule files: •# DRC rules file: /cad/Mentor_tools/umc_018/rule_deck/DRC/G-DF- MIXED_MODE_RFCMOS18-1.8V-3.3V-1P3M_4M_5M_6M-MMC-Calibre-drc-2.8- P1 •# LVS rules file: /cad/Mentor_tools/umc_018/rule_deck/LVS/Calibre.LVS.txt •# SDL rules file: /cad/Mentor_tools/umc_018/process/umc18mmrf_sdl_rules •# PEX rules file: /cad/Mentor_tools/umc_018/rule_deck/LVS/Calibre.LVS.txt EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Creating a Layout Cell View • STEP (1): In ICstudio’s Library window, select the library that contains the Cell whose layout you wish to make. Then select the Cell and click on File>New>View from the menu bar. A window will pop-up asking for the cell view type. Choose Layout as View type. The view name Will be automatically named layout. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay • STEP (2) : By Pressing “Next” a new window will appear asking you for the “connectivity Source”. Select “schematic” to open IC-station in “SDL” (Schematic Driven Layout) mode. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay • STEP (3) : By pressing Finish this will open IC-station. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Creating SDL •Step (1) : Placing the devices : Now there are two ways of placing the Devices in Layout. (i) Manual Pick and place (ii) Auto Pick and Place. These options can be selected from Icon bar. (i) Manual Pick and Place : Click on Pick and Place icon. It will ask for the placement of PMOS and the layout will appear on layout window. Click on the layout window for placing PMOS. Then it will show the layout of NMOS which should be placed in a similar manner. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay (ii) Auto Pick and Place : Click on Auto Pick and Place icon. NMOS and PMOS both will be placed on layout window. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay •Step (2) : Placing PMOS in nwell : Click on the rectangle symbol on left side icon palette and then click on nwell on right side layer palette. Draw nwell surrounding PMOS. The screen looks like this : EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay •Step (3) : Placing the Ports : Select the Place Port icon from icon Bar. It will show you a pop-up window with all ports. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Select the port VDD, select layer ME1. The width and height are selected automatically. Use apply to place VDD. Similarly place the remaining 3 ports. The screen will look like this : EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay • Step 4: Add the substrate Contacts : In the left side icon palette, click on [D] icon. It shows a pop-up window of add Device . Then select Path based guard-band option. It will show another pop-up window as given below. Set width to 1 and select psub and then “OK”. Go to Layout window and draw the Substrate contact. Similarly draw the nwell contact. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay The screen will look like this : Note that the psubstrate Contact has been drawn Over ground thereby Connecting it to ground. Similarly nwell contact is connected to VDD. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay • Step 5 : Routing the layout : We have two options. (i) Auto routing (ii) Manual Routing. • (i) Auto routing : Use View> Toolbars> Show assemble toolbar. The routing toolbar gets added to the icon bar. Click on Auto- routing icon. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay The screen looks like this after Autorouting. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay (ii) Manual Routing : To start routing press IRoute icon in icon bar. Once you place cursor on where you want to start routing, it will start guided by fly lines. You can toggle between connectivity layers by pressing space-bar. The screen looks like this : EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay • Step 6: Labelling nets : After routing we need to label the nets with names used in schematic so that the LVS tool can recognise the nets and compare with schematic. Select Add>Text. Select suitable layer say M1_text for in port. Take the cursor to layout window and left click on the net that you wish to place the text. Similarly label the other ports i.e. OUT, VDD etc. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Verifying the layout design Rules (DRC) : Now we can verify layout by running DRC and LVS checks. We will run Calibre interactive. Running calibre interactive DRC : Select Tools> calibre > Run DRC entry from pull-down menu. The following pop-up window will appear. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay The DRC file is already loaded ( loaded at the time of creating project and creating schematic). Click on run DRC . EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Running Calibre interactive LVS : Go to tools> calibre > run LVS. The following pop-up window will appear. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay The LVS file is already loaded (loaded at the time of creating the project and creating the schematic). Click on run LVS . The RVE window will pop-up and results will look like this. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Parasitic Extraction •After completing DRC and LVS checks we can proceed to extract parasitic capacitance and resistance of the layout. •Click Tools>Calibre>PEX •Check the box Export from schematic viewer under inputs . •Click run PEX EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay The extraction should run, producing PEX netlist like the one below. EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay References www.sharada.ee.iitb.ac.in/~ee705/sugested_reading/umc_kit_user_guide.pdf EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini

IIT Bombay Thank you EE 705/707 Lecture No. 15 Prof. Maryam Shojaei Baghini