Assembly Language Programming Floating-point Computations Zbigniew Jurkiewicz, Instytut Informatyki UW November 28, 2017 Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Representation in IEEE 754 Standard Fraction (mantissa) and exponent S × 2 E In a normalized number the fraction is a “fixed-point” number of the form 1. bbbbbbbbbb... , for example 1 . 0110001110111 × 2 7 Two standard IEEE formats : single precision (32 bits) and double precision (64 bits) Intel FPU additionally has extended precision (80 bits). Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Classes of numbers Classes of numbers: signed zeroes normalized denormalized finite numbers signed infinities NaNs ( Not a Number : just that) indefinite numbers Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Zeroes The sign of zero lets us to find the direction of occured underflow lets us to find the sign of infinity, which a number has been divided by is useful for interval arithmetics Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Normalization Lack of normalization means less precision (smaller number of meaningful binary digits). Receiving denormalized result signals an underflow condition (#U). In Intel FPU: floating-point underflow exception = getting denormalized result floating-point denormal-operand exception = discovery, that the operation operand is a denormalized number. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Infinities Infinities can be compared and used in arithmetic operations. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
NaN Types of NaN: S = 1.0xxxxxxx SNaN (Signaling Nan) as an operand they signal floating-point invalid-operation excep- tion, they have to be created programmati- cally (the procesor does not generate them) m = 1.1xxxxxxx QNaN (Quiet NaN) are allowed (in principle) to be operand in arithmetic operations m = 1.10000000 Floating-point indefinite Usage: The compiler fills noninitialized elements of an array with NaNs containing element index. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
IEEE single precision topmost bit (31) is a sign S next 8 bits (23..30) for exponent E 23 lowest bits (0..22) for fraction F a normalized fraction is always of the form 1. bbbbbbbbbb... , so we save memory by not storing the uppermost 1. an exponent is always shifted (“biased”) by 127. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
IEEE single precision Special cases E = 0 & F = 0: the number 0 (depending on sign +0 or -0) E = 0 & F � = 0: denormalized number E = 255 & F = 0: infinity ( ∞ ) E = 255 & F � = 0: NaN (Not a Number) — indefinite result Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
IEEE double precision the topmost bit (63) contains a sign 11 next bits (52..62) for exponent 52 lowest bits (0..51) for fraction Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Intel technology Initially floating-point computations had been performed on a separate coprocessor called FPU ( Floating Point Unit ). In newer models it has been built into the main processor. MMM technology enabled parallel comptutations on packed integer numbers (small vector processing). First in Pentium MMX and Pentium II. SSE technology was intoduced to permit similar computations on packed single-precision floating-point numbers. It uses separate 128-bit registers. First in Pentium III. SSE2 technology extends it with packed double-precision floating-point numbers and packed integer numbers of different sizes. Also some operations have been added. From Pentium 4. SSE3 only adds additional operations. From Pentium 4HT andi Xeon. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Intel FPU Once it was really a separate chip (so called “mathematical coprocessor”), now embedded, but architectural separation has been preserved in the form of separate computational environment For example FPU instructions cannot touch normal registers (EAX etc.), because this registers are in a “different procesor”. The separate set of registers st0, st1, ..., st7, which form the stack (with st0 on top). Operations (nearly) always use top of stack. The separate state register (“flags”), invisible for the normal processor, and the control register. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
State flags Bits and masks used in two contexts: for FPU instructions x87 FPU status word: bits 0..5 x87 FPU control word: masks 0..5 for SIMD operations in SSE/SSE2/SSE3 instructions MXCSR register: flags in bits 0..5, masks in bits 7..12. State flag bits are “sticky”: once set they state set until cleared by hand. So we may mask ale exceptions and look for exceptional situations after performing the whole computation sequence. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Exceptions In Intel processors there are 6 classes of exceptions with bits and masks for precomputation Invalid operation (#I), bit IE, mask ME. stack overflow or empty stack (#IS) illegal arithmetic operation (#IA), e.g. division ∞ by ∞ or zero by zero Divide-by-zero (#Z), bit IZ, mask MZ etc. Denormalized operand (#D), not in IEEE standard for postcomputation Numeric Overflow (#O) Numeric underflow (#U) Inexact result (precision) (#P), very popular, e.g. 1/3 Setting a mask results in a default handling of the exceptions, otherwise the exception is raised. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Instructions: load and store FLD place Moves the contents of place to the top of the stack. Place may be also an FPU register. FILD place Fetches the integer number from memory, changes to floating-point format and pushes on stack. FLD1 Pushes number 1 on the top of stack. FLDZ Pushes zero on the top of stack. FXCH st n Swaps the contents of a given register and the top of stack. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Instructions: load and store FST place Stores the contents of the top of stack into the given place (which may be also another FPU register. FSTP place The same, but with popping the stack. FIST place Converts the number from the top of stack into 2 or 4-byte long integer and stores in a given place. FISTP place The same, but with popping the stack; it is possible to get 8-byte long number. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Instructions: arithmetics FADD place Adds the contents of place to the top of stack (st0). FADD register ,st0 Adds the contents of the top of stack (st0) to the register . FADDP register ,st0 The same, but with popping the stack. FIADD place Adds the integer number from place to the stack top (st0). Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Example [Carter] Summing the array: SIZE equ 10 section .bss array resq SIZE sum resq 1 section .text mov ecx, SIZE mov esi, array fldz ;initialize st0 lp: fadd qword [esi] ;next element add esi, 8 ;step loop lp fstp qword sum ;store the result Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Instructions: arithmetics For subtraction we have twice more instructions, because it is not the commutative operation, examples: FSUB place Subtracts the contents of place from the stack top (st0). FSUBR register ,st0 Subtracts the contents of the stack top (st0) from the register , the result is in st0. FSUBR TO register Same, but the result is in register . Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Instructions: arithmetics and comparisons Multiplication and division are analogous to addition and subtraction. FCOM place Compares place with the stack top (st0). FCOMP place The same with popping the stack. FCOMPP Compares st0 with st1 and pops both from the stack. FTST Compares st0 with zero. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
Comparison instructions Main processor’s conditional instructions do not look into FPU state register, so we should first copy flags to EFLAGS. FSTSW place Saves state register in a given place, usually in a register AX. Then we can use SAHF instruction to move flags to EFLAGS. For conditional jumps we should use JA, JB and JZ (in other words, we treat floating-point numbers like unsigned integers). Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Floating-point Computations
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