Andrew Frey Western Washington University Electronics Engineering - PowerPoint PPT Presentation

Andrew Frey Western Washington University Electronics Engineering Technology 2010

 MCU: Freescale 9S12C32  32kBytes Flash EEPROM, 2kBytes RAM  24MHz Bus Frequency  Memory Requirements  <10kBytes ROM  1kByte RAM  Resources Used  1 SPI and 1 SCI port  9 GPIO pins

 Kernel  TimeSlice  10ms period  4 Tasks

 CPLD: Xilinx XC2C256  256 Macrocells, 16 Function Blocks  System Frequency: 1MHz  Required Resources  ~30 Macrocells  Resources Used:  8 GPIO pins  Hierarchal VHDL Design  9 VHDL modules (8 for SPI implementation)

First  Different Code States Entered correspond to Button Pressed users actions Main Sleep Menu  Only 1 Mode # state(sleep Inactivity Period mode) not user * defined Lock User Code Management Enter Code Unlock

WaitForSlice  Time Slice Scheduler  10ms period  KeyTask  Checks for keypress  Period: 10ms(sporadic)  Execution Time: ~50µs 

 UITask  Handles input from KeyTask  Updates the LCD screen  Saves user codes  Period: 20ms(sporadic)  Execution Time: ~2ms  RFTask  Configures Registers and sends data packets if valid code has been entered  Period: 100ms  Execution Time: ~500µs

WKDoorLock.c Key.c Keypad I/O KeyInit() Key GetKey() KeyFlag KeyTask()

WKDoorLock.c Key.c LD4Bit.c GetKey() LcdDispStrg() Key UITask() GoodCode FlashSaveCode() RFTask() SaveCode RFModules.c ProgFlash.c

WKDoorLock.c RFModules.c nRF24L01+ TxConfig() nRF24L01Init() Startup LockMsg() RFTask() UITask() GoodCode

 L=Execution Time/Period  L peak = 50µs/10ms + 2ms/20ms + .5ms/100ms = 11%  L avg = 4% based on amount of time in between uses

Module Tasks Functions Data WKDoorLock.c WaitFor Slice() - MsgOut UITask() Code LCD4Bit.c - Lcd4BitInit() RFModules.c RFTask() nRF24L01Init() Good_Code TxConfig() LockMsg() Key.c KeyTask() GetKey() Key KeyInit() ProgFlash.c - FlashSaveCode() UserCode

 Detect_and_signal.vhd  Decodes incoming Signal  Sends signal to motor driver  ~50-75 Macrocells used  Spi_interface.vhd  The master program for SPI implementaion  Consists of 8 other VHDL modules  ~30 Macrocells used

nRF24L01+ Spi_master.vhd Main.vhd Motor Driver MotorBF Spi_interface Detect/Decode

 Macrocell usage:  ~30/256 = 12%

Module Application Detect_and_Signal.vhd Decodes incoming signal. Sends signal to motor driver if the signal was the correct one. Spi_interface.vhd Interconnect structure of the SPI interface portion of the SPI master Sck_logic.vhd Generates an internal SCK by dividing the system clock as determined by CLKDIV. Upcnt5.vhd 5-bit counter Upcnt4.vhd 4-bit counter Spi_xmit_shift_reg.vhd Shift register that shifts data out on MOSI. 8 bit-shift register clocked on the SCK Spi_rcv_shift_reg.vhd Shift register that shifts data in on MISO. 8-bit shift register clocked on the SCK. Spi_control_sm.vhd Overall control of the SPI interface. Generates SS and control signals to the shift registers.