Advanced technology for ILC Calorimeters Readout and DAQ parts NANNI Jérôme Electronics engineer Laboratoire Leprince Ringuet (France) KEK seminar 2017, December 12
Electronics challenges for ILC ECAL DAQ introduction Electronics development Beam tests results Next steps Feeding others projects nanni@llr.in2p3.fr - KEK seminar - 2017December12 2
Preview of prototypes NEW ELECTRONICS 2 nd prototype DESIGN 6 layers ~ 6k channels 1st prototype 30 layers ~ 10k channels Construction Proof of concept Feasibility of design options • Linearity • Compactness • Integration • Resolution • Granularity • Environment • Sensors • Front-end • Services • Very front-end • Power pulsing • Industrialization • Long SLAB • Tooling Last prototype • Project org. Time 10 layers ~ 10k channels nanni@llr.in2p3.fr - KEK seminar - 2017December12 3
Introducing the DAQ Calicoes CCC board C lock and C ontrol C ard ASU board FEV board A ctive F ront E nd wafers S ensor U nit B oard GDCC board G igabyte D ata C oncentrator C ard SMB board SLAB DIF board D ectector S weat M ain B oard I nter F ace nanni@llr.in2p3.fr - KEK seminar - 2017December12 4
Calicoes • Highly modular and distributed • Control the Ecal electronics but also the peripheral devices (Power supply, pulse generator,…) • Provides a high level state machine for final user • Scripting language (Python) • Good stability Global control-command architecture nanni@llr.in2p3.fr - KEK seminar - 2017December12 5
Calicoes Load connectivity Destroy memory Allocate memory structures structures Reset device Load configuration Power off high voltage Configure devices Close connections Synchronize clocks Power on high voltage Start acquisition Stop acquisition signals signals Flush files Documentation: http://llr.in2p3.fr/sites/pyrame/calicoes/documentation/index.html nanni@llr.in2p3.fr - KEK seminar - 2017December12 6
GDCC (Gigabyte Data Concentrator Card) CCC (Clock and Control Card) CCC Board Able to connect 7 DIF - Base on Xilinx Spartan XC6SLX75 - Marvell component for Ethernet FPGA DIFs GEMAC ETHERNET MARVELL Main TO - Until 8 HDMI connections Links Interface (Protocol - Synchronize all sub-systems (based on DIF fsm - Distribute asynchronous several ser-des MCLK trigger/busy signals FSM) 8b/10b) CCC interface - Capable to distribute clock TRIG GDCC 50MHz nanni@llr.in2p3.fr - KEK seminar - 2017December12 7
DIF (Detector InterFace to the DAQ) Goal: connect the detector to control and DAQ system by serial link synchronous to 40MHz. - Condition signals to VFE chips - Configuration - Readout - Generate clock 2.5MHz for ReadOut - Get information like board status, firmware version … Able to read several thousands of detector channels up to 13000. Able to read different chips for many experiments in our laboratory. nanni@llr.in2p3.fr - KEK seminar - 2017December12 8
SMB (Sweat Main Board) Goal: condition signals for VFE chips, power supply and clock integrity. FEV Regulator for connector Analogue and Digital power supply DIF connector Big capacitance (300mF) to Buffer to drive the absorb the dynamic power clocks 40MHz and supply current, design for 1 ms 2.5MHz acquisition in the barrel. nanni@llr.in2p3.fr - KEK seminar - 2017December12 9
FEV board (Front End Board) 1024 pixels - Read energy of 1024 pixels - Slow Control for 16 Skiroc2 - Readout for 2 partitions of 8 chips - 2 power supply (analogue & digital) - 16 layers Pedestal FEV board (bottom view) MIP Glued wafers 16 Skiroc2 chip FEV board (top view) nanni@llr.in2p3.fr - KEK seminar - 2017December12 10
Skiroc chip SKIROC: S ilicon K alorimeter I ntegrated R ead O ut C hip - SILICON SENSORS (325µm thick) : 26000e - /MIP - C detector estimated 9pF + 10pF for PCB pad’s - PIN diode leakage up to 10nA / channel - Ultra low power - 64 channels consumption (to Minimize - 250 pads cooling) 25 µW/ch with - Technology: AMS SiGe 0.35µm Full Power Pulsing - Size: 65mm² - Very low noise: 2500e - (0.4fC) - 1 MIP = 4fC - Dynamic range: 0.4fC 10pC nanni@llr.in2p3.fr - KEK seminar - 2017December12 11
Skiroc chip Fast shaper noise studies Scurves vs threshold Preamplifier DC level uniformity rms noise= 5.3 mV ie 1/9 MIP S/N>9 DC PreAmplifier SKIROC2 2,02 2,01 2 1,99 1,98 DC (V) 1,97 Pedestal=167 DAC Units 1 Mip ≈4 fC = 20 DAC Units 1,96 Noise= 2 DAC Units 1,95 1,94 <>=1.969 V rms=1.5 mV 1,93 1,92 0 10 20 30 40 50 60 Channel nanni@llr.in2p3.fr - KEK seminar - 2017December12 12
First tests of ASU bench There is a specific bench to test FEV board before gluing. Possibility to place a wafer, a mechanic interface and the FEV board. Goal: verify all chip answered, pcb as no shortcut. Also, it’s interesting to estimate noise on each chip. nanni@llr.in2p3.fr - KEK seminar - 2017December12 13
Scurves, noisy channels Instead activated all channel, run 8 by 8. Reduce effect of crosstalk. Masked channel Uniform noise around 220-240uDAC. Reproducible measure in time. Number of hit Number of hit After masking channel Trigger threshold reduced. Trigger (uDAC) Trigger (uDAC) nanni@llr.in2p3.fr - KEK seminar - 2017December12 14
Introduce short SLAB Goal: first studies to improve design. - Be able to detect a MIP ( M inimum I onization P article) - Configure all chip compare to noise - Have adapted signals for clock and control - Get a S/N > 10 Aluminium cover - Read raw data in few ms. FEV board ( F ront E nd V ersion) Thermic layer (copper) SMB board ( S weat M ain B oard) DIF board ( D etector I nter F ace) High Voltage kapton Carbon structure in U nanni@llr.in2p3.fr - KEK seminar - 2017December12 15
Short SLAB Get a final layer design include chips, PCB, wafer … Thickness of electronics < 4mm (half alveolar size) Kapton interconnector HV connector nanni@llr.in2p3.fr - KEK seminar - 2017December12 16
Last prototype Compact detector Include up to 10 layers Possibility to place Tungsten between each layer Connect each power supply by a front panel. Auto-masking of noisy channels: Every layers are adjusted in laboratory with optimize scripts. 10 layers adjusted in 3h !!! nanni@llr.in2p3.fr - KEK seminar - 2017December12 17
Test beam 2017 @DESY Excellent results, S/N~20 better than 2015. Pedestal position dispersion for all channels (~6 ADC) Concept is validate next step LONG SLAB S/N ratio for all SLABS S/N = 20 ; Dispersion = 7,8% Test beam performance presentation: https://indico.cern.ch/event/629521/contributions/2703010/ nanni@llr.in2p3.fr - KEK seminar - 2017December12 18
Event Display Compact shower + “cosmic” Shower (event layer/layer) nanni@llr.in2p3.fr - KEK seminar - 2017December12 19
ILD Slab (for final detector) For ILD 8 to 12 ASU / layer Layer length = 2.2 meters Many challenges: - Interconnection solution - Kapton - Connector - Propagate signal on 3 meters - Clock (delay, load, attenuation, …) - Control signals - ReadOut (data integrity, amount of data) - Power distribution ? - Power tree - cross board - Mechanical structure - Design with minimize distortion - Weigh - Transportation nanni@llr.in2p3.fr - KEK seminar - 2017December12 20
ILD Slab (for final detector) 12 ASU full equipped of wafer 120k€ Need to make physics with less cost Use mini wafer (4x4 pixels instead of 16x16) Alpha source put under the long slab for physics Scurves analysis for baby wafer glue on long slab 21 nanni@llr.in2p3.fr - KEK seminar - 2017December12
ILD Slab (for final detector) New mechanical structure, able to receive 12 ASU Total length 3m System to place ASU on structure with 3d printed nanni@llr.in2p3.fr - KEK seminar - 2017December12 22
CALICE TO WAGASCI Location: J-PARK neutrino beam, JAPAN Physics goal: Cross section ratio measurement between H2O/CH for charged-current interaction with different Neutrino energy ranges. 40 MPPC 40 ASU 2 DIF nanni@llr.in2p3.fr - KEK seminar - 2017December12 23
CALICE TO HGCAL CMS DIF board SMB+FEV board Base on Calice design: GDCC board 2 pcb layers - read out: 4 chip SKIROC2cms, 4x32 channels - FPGA: ALTERA MAX10 - sensor (200µm, 6” silicon wafer) nanni@llr.in2p3.fr - KEK seminar - 2017December12 24
Summary Electronics and instrumentation department of LLR develop many prototypes (conception, production and tests), with high technology and good performances. The results of ILD Slab in the next test beam will shows the ability to instrument 2.2 meters active layer (readout, clock, power, data integrity, …). LLR DAQ is generic and adapt for many experiments, local, international (HGCAL CMS) and with Japan (T2K WAGASCI) on innovative and complex projects of detector. LLR able to solve Electronics, DAQ, instrumentation Challenges, in a context of international project with R&D phase, tests definition, proposal solutions. … nanni@llr.in2p3.fr - KEK seminar - 2017December12 25
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