A Structured Routing Architecture and its Design Methodology Suitable for High-throughput Electron Beam Direct Writing with Character Projection Rimon IKENO 1 , Takashi MARUYAMA 2 , Tetsuya IIZUKA 3 , Satoshi KOMATSU 1 , Makoto IKEDA 1 , and Kunihiro ASADA 1 1 VLSI Design and Education Center (VDEC), The University of Tokyo, 2 e-Shuttle, Inc., 3 Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo
Agenda Introduction Structured Routing Architecture and Stencil Design SRA Design Methodology Experimental results Conclusion 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 2
Agenda Introduction Structured Routing Architecture and Stencil Design SRA Design Methodology Experimental results Conclusion 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 3
Introduction Electron-Beam Direct Writing (EBDW) Low-cost ‘maskless’ exposure solution Mask cost explosion in high-resolution lithography Low exposure throughput One figure per one EB shot (dot, rectangle, ..) Limited applications : low-volume products, test chips, ... EBDW with Character Projection （ CP ） technique Promising high-throughput EBDW in 14nm and beyond Shooting multiple figures at once as a character Characters = “Frequently - appeared layout patterns” Prepared on character stencil Higher CP throughput = More figures in 1 EB shot More character varieties required! 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 4
Overview of Character Projection (CP) EBDW Shot count comparison CP EBDW equipment Variable Shaped Beam Character Projection beam source (VSB) (CP) electron beam 1 2 1st aperture Stencil area (beam shaping) 1 limitation 2nd aperture 3 6 (character stencil) characters 4 5 wafer (resist) exposed character 6x faster throughput Limited character variety (number) CP efficiency (E CP ) = 6.0 ) Challenges toward the practical CP EBDW use: Shot# reduction: >1000 G-shot/wafer (VSB) ~100 Gs/w (= E CP >10 ) Char# suppression: covering any layout patterns with limited characters 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 5
Agenda Introduction Structured Routing Architecture and Stencil Design SRA Design Methodology Experimental results Conclusion 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 6
Structured Routing Architecture (SRA) Purpose: to reduce VIA/metal CP character variations while increasing the figure# in each EB shot Periodic track grouping, and restricted track exchange VIA placement on diagonal lines Less VIA characters Limited metal segment shapes Less metal characters Limitations in routing flexibility & cell port accessibility Track-assign-first flow / switch layer insertion 4 3 2 1 4 3 2 1 1 2 3 4 1 2 3 4 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 7
Metal and VIA Layer Usage in SRA Structured routing layer Routing layers (Regular segments) (structured tracks VIA & diagonal VIA) (Diagonal arrangement) Track port layer (Tile metal segments) VIA Switch layers (Virtual) tile cells (port-track conn.) Cell ports (regular shape) Cell layer 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 8
VIA Array Characters and Stencil Design Diagonal VIA array characters (binary codes) Overlapped pattern “11101” “11010” “10101” “1110101∙ ∙ ∙” VIA & vacancy alignment VIA character arrangement on stencil EB shot area Pattern division & arrangement char. size [grid] 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 9
Metal Segment Characters and Stencil Design Metal wire layout with diagonal VIA Metal segment character arrangement on stencil EB shot area Metal segment character examples 2 2 1 2 Char. size 2 1 (height) 2 2 “2210” “2122” Character Seg. length ‘0’ overlap blank ‘1’ Segment length pad ‘2’ + character size – 1 span 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 10
Agenda Introduction Structured Routing Architecture and Stencil Design SRA Design Methodology Experimental results Conclusion 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 11
Overview of Routing Design Flow for SRA (i) tile netlist construction Netlist & cell cell library placement tile netlist (ii) net coloring & netlist decomposition node color tile netlist tile netlist (track) info (color #1) (color #n) (iv) port-track (iii) routing routing local connection routed design routed design local (color #n) (color #1) interconnects (v) routing result superposition routed design (all) 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 12
Track Assignment by Tile Netlist Coloring Input netlist & cell placement Tile netlist generation & coloring node A Tile 1 Tile 4 Tile 3 node C Tile 2 Tile 5 node B Graph modeling & node coloring Partial netlist generation Tile 4 Color #1 Color #2 node A Tile 1 Tile 1 Tile 3 Tile 2 Tile 3 Tile 3 node C Color #3 Color #4 Tile 4 Tile 2 node B Tile 3 Tile 2 Tile 5 Tile 5 Tile 4 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 13
Partial Netlist Routing and Layout Integration Color #1 Color #2 Color #3 Color #4 Partial Tile 4 Tile 2 netlists Tile 1 Tile 3 Tile 2 Tile 3 Tile 3 Tile 5 Tile 4 Automated routing Track #1 Track #2 Track #3 Track #4 Partial layouts Layout integration Unified layout No layout conflicts due to the dedicated tracks 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 14
Agenda Introduction Structured Routing Architecture and Stencil Design SRA Design Methodology Experimental results Conclusion 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 15
Experiments and CP Throughput Evaluation Experiments: Reference designs (Conventional P&R / 65nm) Netlist & cell placement SRA design flow CP throughput evaluation CP throughput evaluation: Shot count estimation per wafer average shot area (100Gs/w) × target shot count 10 . 0 100 = total shot area (G shot/wafer ) (shot# ) (layout area) Evaluation criteria: Practical shot count in 14nm = 100~173 Giga shot/wafer 173 Gs/w: the minimum throughput requirement 100 Gs/w: the target to allow margins of other factors 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 16
Tile-cell Netlist Generation and Node Coloring SRA design steps: 8080 USB 2.0 AES Discrete Design Compat. Function Cosine Tile-cell netlist gen. (Rijndael) name CPU Core IP Core Trans. Graph modeling Logic cell# 4,326 7,708 16,755 13,880 Graph (net) coloring Tile cell# 3,479 8,316 16,859 17,597 (Brelaz, et. al, 1979) Track assignment Signal net# 4,346 8,077 17,014 14,297 & Partial netlist gen. 1 829 1,747 4,115 3,623 2 787 1,554 3,720 3,048 3 726 1,311 3,122 2,438 Coloring results: 4 665 1,299 2,407 2,068 Successful coloring Net# per 5 597 1,114 1,795 1,496 with the limited track color colors (Tile size L=9) 6 523 745 1,338 1,063 Unbalanced net# for 7 204 261 502 414 each assigned color 8 15 38 14 133 Partial netlists: to be 9 0 8 1 14 used in the next step Max. color 8 9 9 9 (partial routing) Tile size = 9 grid (= lib cell height) 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 17
Partial Netlist Routing Results Track #2 Track #7 Tile cell Tile cell Separate interconnect routing (ICC) results of the partial netlists Routing only on the assigned tracks Sparse routing results on the square grids 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 18
Routing Result Superposition for All Tracks All tracks (all layers) All tracks (VIA4, Met5) Tile cell Tile cell Superposition of the routing results of the partial netlists No conflicts due to the dedicated tracks for each partial results Diagonal VIA arrangement Regular-length metal segments with diagonal arrangement 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 19
Routing Length Comparison: Ref vs. SRA Wire length in each layer (USB 2.0) Total wire length: SRA/Ref 140% Reference SRA 118.2% 120% Wire length ratio (SRA/ref) Layer Length [um] Layer Length [um] 109.0% 97.3% MET1 1,079.6 <MET4 43.2 100% 83.0% MET2 15,879.8 MET4 17,398.8 80% MET3 37,475.9 MET5 40,914.0 MET4 31,732.7 MET6 34,495.2 60% MET5 30,313.6 MET7 25,819.2 40% MET6 18,980.9 MET8 15,049.8 >MET6 9,573.9 >MET8 7,374.6 20% Total 145,036.3 Total 141,094.8 0% Ratio (SRA/reference) 97.3% 8080 USB AES DCT Design Higher layers used in SRA due to the switch layer insertion As for the routing layers, slightly shorter wires in SRA (USB 2.0) despite the coarse routing grids and the reduced routing flexibility SRA required -20~20% wires than ref in the 4 example designs 2013/3/26 R.Ikeno / VDEC, Univ. Tokyo 20
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