A Configurable Hardware Scheduler A Configurable Hardware Scheduler (CHS) for Real- -Time Systems Time Systems (CHS) for Real Pramote Kucharoen, Mohamed A. Shalan and Vincent J. Mooney III Center for Research on Embedded Systems and Technology School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia, USA 23 June 2003
Outline Outline • Introduction • Related work • CHS architecture • CHS commands • CHS interface • Software support • Automatic customization of CHS • Experiments and results • Conclusion 2
Introduction Introduction Real-time system layers Application 1 Application 2 Application Application Task1 Task2 Task3 Task1 Task2 Task3 RTOS Core Time Task CHS Support Scheduler RTOS Hardware CPU Memory I/O Hardware 3
µ µ µ µ C µ µ µ µ C/OS II Background Processing /OS II Background Processing ptcb = OSTCBList; /* Point at first TCB in TCB list */ while (ptcb->OSTCBId != OS_TASK_IDLE_ID) { /* Go through all TCBs in TCB list */ OS_ENTER_CRITICAL(); NOT FIXED-CYCLE OPERATIONS if (ptcb->OSTCBDly != 0) { /* Delayed or waiting for event with TO */ if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ Number of Tasks Dependent if (!(ptcb->OSTCBStat & OS_STAT_SUSPEND)) /* Is task suspended? */ OSSched(ptcb,RDY); else /* Yes, Leave 1 tick to prevent loosing */ ptcb->OSTCBDly = 1; /* the task when the suspension is removed. */ } } ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ OS_EXIT_CRITICAL(); } 4
µ C µ µ µ Overhead in µ µ µ µ C/OS II Scheduler /OS II Scheduler Overhead in 45% 40% 64 tasks 35% Time tick Resolution 30% Overhead % 25% Dependence 32 tasks 20% 15% 16 tasks 10% 8 tasks 5% 4 tasks 0% 10 100 1000 Time tick resolution (usec) 5
Related Work Related Work Only One Only One Scheduling Scheduling Inflexible Inflexible Discipline Discipline Packet Packet Scheduler Scheduler FASTCHART FASTHARD FASTCHART FASTHARD Not for Not for Adaptive Adaptive Systems Systems 6
Why do we need the CHS? Why do we need the CHS? • To reduce the scheduling overhead from the real- time operating system; hence, improve the system response time • To support a wide range of applications by supporting multiple scheduling disciplines that can be changed during system execution time. – Priority – Earliest Dead Line First (EDF) – Rate Monotonic (RM) 7
CHS Architecture (1) CHS Architecture (1) Tasks Tasks SQ PQ SQ PQ Table Table Current Task Current Task I nt 0 Control Signals I nt 1 I nterrupt . I nterrupt . . Controller Controller . Control Unit . I nt 7 Control Unit Bus I nterface Signals 8
CHS Architecture (2) CHS Architecture (2) Priority Queue (Ready Queue) REG + Counter REG + Counter REG + Counter REG + Counter Comparator LOGI C Comparator LOGI C Comparator LOGI C Comparator LOGI C Comparison results from the right block Comparison Results New Data I D Register Counter 9
CHS Architecture (3) CHS Architecture (3) Sleep Queue • Used to store the Sleeping Tasks (YIELD/SLEEP). • The Tasks are sorted according to their remaining sleep time. • Once The Sleep Time expires it is moved to the PQ. I D Counter 10
CHS Architecture (4) CHS Architecture (4) Task Table • Store Information about the existing tasks • Indexed by the Task ID PRI Period WCET TYPE PRE STATUS 11
CHS Commands CHS Commands Command # of Cycles STOP 1 Scheduler Related RUN 1 CONFIGURE 1 CREATE Task 1 MODIFY Task 2 SLEEP 2 SSLEEP 1 Task Related YIELD 1 SUSPEND 1 RESUME 1 DELETE 1 12
CHS Interface CHS Interface The CHS Hardware is designed to be able to interface easily to any microprocessor core: – As a memory mapped I/O Port, – As a co-processor, or – As instruction-set accelerator 13
Software Support Software Support APIs • Task – createTask – suspendTask, resumeTask – changePriority, changeWCET, changePeriod – Yield – ssleep, sleep • Scheduler – configureScheduler – enableScheduler, disableScheduler 14
Automatic Customization of CHS Automatic Customization of CHS HW SW HW SW VPP VPP DB DB Customized DB DB Customized HW HW Customized Customized SCon SCon RTOS RTOS DC DC Synthesis Synthesis Script Script 15
Experiments and Results (1) Experiments and Results (1) Simulation Environment VCS Seamless CVE XRAY VCS Seamless CVE XRAY Hardware Interrupt Hardware MPC750 MPC750 Scheduler Scheduler Address/Data Bus Memory Memory 16
Experiments and Results (2) Experiments and Results (2) Assembly instruction execution comparison Micro C/OS II Hardware Scheduler Scheduler* 69 0 Time-tick processing 47+47*(number of tasks) 0 * Priority Scheduler Number of PowerPC instruction of the APIs API # of PPC Assembly WCET (# of cycles) Instructions configureScheduler 37 230 SuspendTask 21 125 CHS Requires One PPC Instruction to be Configured and One Instruction to Suspend a Task which means over 100x Speedup. 17
Experiments and Results (3) Experiments and Results (3) Scheduling in Time tick Scheduling in Time tick background background Software processing Software processing CHS CHS Fixed-Cycle Fixed-Cycle Operations Improve Response Time Operations Improve Response Time 18
CHS Synthesis Results CHS Synthesis Results Area (mm 2 ) Number of standard cells 1115 0.24 Using HP 0.35 µ µ process µ µ Number of Logic Elements Number of Registers 421 564 Using Altera Quartus II for EP20K The Synthesized CHS Supports – 16 Tasks and – up to 8 interrupt sources 19
Conclusion Conclusion • We implemented a configurable hardware scheduler that supports 3 scheduling algorithms • We developed software interface for the configurable hardware scheduler and a tool to generate a customized synthesizable CHS • The configurable hardware scheduler eliminated the time spent by the processor for background time tick processing and scheduling 20
Questions? Questions? 21
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