Kuo-Feng Hsu* , Praveen Tammana + , Ryan Beckett # , Ang Chen*, Jennifer Rexford + , David Walker + Rice University*, Princeton University + , Microsoft Research # 1
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Traffic flows src1 src1 dest dest src2 src2 load = 0 load > 0 3
Probes Probes src1 src1 Best path dest dest Traffic flows Unclear how these solutions can be realized Overloads the best path when RTTs are large using commodity data planes 4
Data structure Question How to balance load dynamically across multiple paths in the data plane? Contributions 1. We design new data structures for load-aware traffic splitting 2. We characterize and study tradeoffs of these data structures 3. We propose a data structure called DASH 5
Weights(1:3) (1) Spreading flows using a Path-to-Weight Data data structure structure Traffic flows Weights(1:3 ) 2:2 (2) Updating that data structure Data structure as probes arrive Probe 6
Per-stage registers Programmable Parser Match + Action pipeline stages 7
2. No access to registers mapped to a different stage 1. Limited #per-packet register accesses Packet Packet 3. Small #stages and limited computation in each stage 8
Replicates table entries with same pathID in proportion to its weight Weight vector Paths: A, B, and C 1 : 2 : 3 A C How can we update B Hash value Packet the table as probes arrive? Hash header C C B WCMP table is stored in a stage registers 9
Iterate over the table A A C A B A C B C B B C Requires many per-packet accesses to a stage registers 10
Assign entries of non-deficit paths to deficit paths Count Path Count Count 3 A 1 2 2 B 2 2 1 C 3 2 A A A C A A A 3 B B B B 2 C A C C 1 C C C B B B Requires read and write to same register from different stages 11
Replicate pathID in WCMP table Idea: Partition hash space into unique regions of size proportion to path weights Boundaries are stored in per-stage registers Weight vector A B C 1 : 2 : 3 H = Hash Packet value H < 1 H < 3 H < 6 Hash header Stage 1 Stage 2 Stage 3 Check packet’s hash value against boundaries 12
New path boundary = Previous path’s boundary + Path region size Desired vector = 3 : 2 : 1 A B C Used per-stage SALUs to 3+2=5 5+1=6 0 0+3=3 execute addition operation 0+3=3 3+2=5 5+1=6 Probe Stage 1 Stage 2 Stage 3 One per-packet access to stage registers Fast and efficient Read-write in the same stage 13
• Symmetric Fattree • CP • 8 Hula ECMP • FCT (sec) DASH 4 • • 2 • • • 10 30 50 70 90 Network load (%) 14
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