1
play

1 6/17/2011 Introduction Emulation Evaluation Conclusions CPU - PowerPoint PPT Presentation

1 6/17/2011 Introduction Emulation Evaluation Conclusions CPU Device Chipset Memory Physical Address Physical Address 2 6/17/2011 Introduction Emulation Evaluation Conclusions Main Memory Physical Address IOMMU MMU I/O Virtual


  1. 1 6/17/2011

  2. Introduction Emulation Evaluation Conclusions CPU Device Chipset Memory Physical Address Physical Address 2 6/17/2011

  3. Introduction Emulation Evaluation Conclusions Main Memory Physical Address IOMMU MMU I/O Virtual Virtual Address Address I/O CPU Device

  4. Introduction Emulation Evaluation Conclusions 4 6/17/2011

  5. Introduction Emulation Evaluation Conclusions 5 6/17/2011

  6. Introduction Emulation Evaluation Conclusions 6 6/17/2011

  7. Introduction Emulation Evaluation Conclusions Guest Domain Emulation Domain System Domain (Hypervisor) Memory 2. Allocate IOVA 3. Update Mappings (IOVA  GPA) Mapping Layer Emul. PTEs 5. Read Phys. PTEs IOMMU 4. IOTLB Invd. of IOVA Emulation 7. Map I/O Buffer IOVA  HPA 6. Pin pages 11. Translate IOVA 12. HPA Access 8. IOTLB Invd. IOMMU 1. Request IOVA for GPA 10. IOVA Access 9. Transaction to IOVA I/O Device I/O Device Driver 7 6/17/2011

  8. Introduction Emulation Evaluation Conclusions 8 6/17/2011

  9. Introduction Emulation Evaluation Conclusions 9 6/17/2011

  10. Introduction Emulation Evaluation Conclusions Write Poll Emulate Guest Emulated Sidecore Done Registers (VMM) Done (Write) Hypervisor (Read) (VMM) 10 6/17/2011

  11. Introduction Emulation Evaluation Conclusions 11 6/17/2011

  12. Introduction Emulation Evaluation Conclusions 12 6/17/2011

  13. Introduction Emulation Evaluation Conclusions I/O virtual page 1 Physical page I/O virtual page 2 13 6/17/2011

  14. Introduction Emulation Evaluation Conclusions 14 6/17/2011

  15. Introduction Emulation Evaluation Conclusions 15 6/17/2011

  16. Introduction Emulation Evaluation Conclusions CPU Cycles SW/HW Logic Total Interaction Bare-metal 2316 4593 6909 Trap & Emulate 30645 4324 34969 Sidecore 7321 1904 9225 Average breakdown of (un)mapping a single page using the strict invalidation scheme 16 6/17/2011

  17. Introduction Emulation Evaluation Conclusions Setting Secure Relaxed Optimistic (No IOTLB (Linux Default; (Patched; IOTLB Batching) IOTLB Batching) Batching) Bare-metal 43% 91% 100% Trap & Emulate 10% 11% 82% Sidecore 30% 49% 100% Measuring the NetperfTCP throughput relatively to the maximum attainable (9.3Gbps) 17 6/17/2011

  18. Introduction Emulation Evaluation Conclusions Setting Secure Relaxed Optimistic (No IOTLB (Linux Default; (Patched; IOTLB Batching) IOTLB Batching) Batching) Bare-metal 84% 92% 94% Trap & Emulate 38% 39% 56% Sidecore 61% 63% 66% Measuring Apache throughput (25 concurrent requests); the baseline for normalization is 6828 requests per second 18 6/17/2011

  19. Introduction Emulation Evaluation Conclusions 19 6/17/2011

Recommend


More recommend